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[Qemu-devel] [PATCH v6 16/77] target/mips: Add nanoMIPS DSP ASE opcodes
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v6 16/77] target/mips: Add nanoMIPS DSP ASE opcodes |
Date: |
Thu, 2 Aug 2018 16:16:03 +0200 |
From: Stefan Markovic <address@hidden>
Add nanoMIPS opcodes for DSP ASE instruction pools and instructions.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 142 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 142 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bbe8b8a..c1843c1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16154,8 +16154,127 @@ enum {
/* POOL32Axf instruction pool */
enum {
+ NM_POOL32AXF_1 = 0x01,
+ NM_POOL32AXF_2 = 0x02,
NM_POOL32AXF_4 = 0x04,
NM_POOL32AXF_5 = 0x05,
+ NM_POOL32AXF_7 = 0x07,
+};
+
+/* POOL32Axf_1 instruction pool */
+enum {
+ NM_POOL32AXF_1_0 = 0x00,
+ NM_POOL32AXF_1_1 = 0x01,
+ NM_POOL32AXF_1_3 = 0x03,
+ NM_POOL32AXF_1_4 = 0x04,
+ NM_POOL32AXF_1_5 = 0x05,
+ NM_POOL32AXF_1_7 = 0x07,
+};
+
+/* POOL32Axf_2 instruction pool */
+enum {
+ NM_POOL32AXF_2_0_7 = 0x00,
+ NM_POOL32AXF_2_8_15 = 0x01,
+ NM_POOL32AXF_2_16_23 = 0x02,
+ NM_POOL32AXF_2_24_31 = 0x03,
+};
+
+/* POOL32Axf_7 instruction pool */
+enum {
+ NM_SHRA_R_QB = 0x0,
+ NM_SHRL_PH = 0x1,
+ NM_REPL_QB = 0x2,
+};
+
+/* POOL32Axf_1_0 instruction pool */
+enum {
+ NM_MFHI = 0x0,
+ NM_MFLO = 0x1,
+ NM_MTHI = 0x2,
+ NM_MTLO = 0x3,
+};
+
+/* POOL32Axf_1_1 instruction pool */
+enum {
+ NM_MTHLIP = 0x0,
+ NM_SHILOV = 0x1,
+};
+
+/* POOL32Axf_1_3 instruction pool */
+enum {
+ NM_RDDSP = 0x0,
+ NM_WRDSP = 0x1,
+ NM_EXTP = 0x2,
+ NM_EXTPDP = 0x3,
+};
+
+/* POOL32Axf_1_4 instruction pool */
+enum {
+ NM_SHLL_QB = 0x0,
+ NM_SHRL_QB = 0x1,
+};
+
+/* POOL32Axf_1_5 instruction pool */
+enum {
+ NM_MAQ_S_W_PHR = 0x0,
+ NM_MAQ_S_W_PHL = 0x1,
+ NM_MAQ_SA_W_PHR = 0x2,
+ NM_MAQ_SA_W_PHL = 0x3,
+};
+
+/* POOL32Axf_1_7 instruction pool */
+enum {
+ NM_EXTR_W = 0x0,
+ NM_EXTR_R_W = 0x1,
+ NM_EXTR_RS_W = 0x2,
+ NM_EXTR_S_H = 0x3,
+};
+
+/* POOL32Axf_2_0_7 instruction pool */
+enum {
+ NM_DPA_W_PH = 0x0,
+ NM_DPAQ_S_W_PH = 0x1,
+ NM_DPS_W_PH = 0x2,
+ NM_DPSQ_S_W_PH = 0x3,
+ NM_BALIGN = 0x4,
+ NM_MADD = 0x5,
+ NM_MULT = 0x6,
+ NM_EXTRV_W = 0x7,
+};
+
+/* POOL32Axf_2_8_15 instruction pool */
+enum {
+ NM_DPAX_W_PH = 0x0,
+ NM_DPAQ_SA_L_W = 0x1,
+ NM_DPSX_W_PH = 0x2,
+ NM_DPSQ_SA_L_W = 0x3,
+ NM_MADDU = 0x5,
+ NM_MULTU = 0x6,
+ NM_EXTRV_R_W = 0x7,
+};
+
+/* POOL32Axf_2_16_23 instruction pool */
+enum {
+ NM_DPAU_H_QBL = 0x0,
+ NM_DPAQX_S_W_PH = 0x1,
+ NM_DPSU_H_QBL = 0x2,
+ NM_DPSQX_S_W_PH = 0x3,
+ NM_EXTPV = 0x4,
+ NM_MSUB = 0x5,
+ NM_MULSA_W_PH = 0x6,
+ NM_EXTRV_RS_W = 0x7,
+};
+
+/* POOL32Axf_2_24_31 instruction pool */
+enum {
+ NM_DPAU_H_QBR = 0x0,
+ NM_DPAQX_SA_W_PH = 0x1,
+ NM_DPSU_H_QBR = 0x2,
+ NM_DPSQX_SA_W_PH = 0x3,
+ NM_EXTPDPV = 0x4,
+ NM_MSUBU = 0x5,
+ NM_MULSAQ_S_W_PH = 0x6,
+ NM_EXTRV_S_H = 0x7,
};
/* POOL32Axf_{4, 5} instruction pool */
@@ -16176,6 +16295,29 @@ enum {
NM_WAIT = 0x61,
NM_DERET = 0x71,
NM_ERETX = 0x79,
+
+ /* nanoMIPS DSP instructions */
+ NM_ABSQ_S_QB = 0x00,
+ NM_ABSQ_S_PH = 0x08,
+ NM_ABSQ_S_W = 0x10,
+ NM_PRECEQ_W_PHL = 0x28,
+ NM_PRECEQ_W_PHR = 0x30,
+ NM_PRECEQU_PH_QBL = 0x38,
+ NM_PRECEQU_PH_QBR = 0x48,
+ NM_PRECEU_PH_QBL = 0x58,
+ NM_PRECEU_PH_QBR = 0x68,
+ NM_PRECEQU_PH_QBLA = 0x39,
+ NM_PRECEQU_PH_QBRA = 0x49,
+ NM_PRECEU_PH_QBLA = 0x59,
+ NM_PRECEU_PH_QBRA = 0x69,
+ NM_REPLV_PH = 0x01,
+ NM_REPLV_QB = 0x09,
+ NM_BITREV = 0x18,
+ NM_INSV = 0x20,
+ NM_RADDU_W_QB = 0x78,
+
+ NM_BITSWAP = 0x05,
+ NM_WSBH = 0x3d,
};
/* PP.SR instruction pool */
--
1.9.1
- [Qemu-devel] [PATCH v6 06/77] target/mips: Add CP0 BadInstrX register, (continued)
- [Qemu-devel] [PATCH v6 06/77] target/mips: Add CP0 BadInstrX register, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 07/77] target/mips: Add gen_op_addr_addi(), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 08/77] target/mips: Don't update BadVAddr register in Debug Mode, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 09/77] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 10/77] elf: Remove duplicate preprocessor constant definition, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 11/77] elf: Add ELF flags for MIPS machine variants, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 12/77] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 13/77] linux-user: Add preprocessor availability control to some syscalls, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 14/77] target/mips: Add preprocessor constants for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 15/77] target/mips: Add nanoMIPS base instruction set opcodes, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 16/77] target/mips: Add nanoMIPS DSP ASE opcodes,
Stefan Markovic <=
- [Qemu-devel] [PATCH v6 17/77] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 18/77] target/mips: Add nanoMIPS decoding and extraction utilities, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 19/77] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 20/77] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 21/77] target/mips: Add emulation of nanoMIPS 16-bit shift instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 22/77] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 23/77] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Stefan Markovic, 2018/08/02