Re: [Qemu-devel] [PATCH v7 42/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4

[Aleksandar Markovic]

> From: Aleksandar Markovic <address@hidden>
> Sent: Monday, August 6, 2018 7:00 PM
> From: Stefan Markovic <address@hidden>
> 
> Add emulation of DSP ASE instructions for nanoMIPS - part 4.
> 
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> ---
>  target/mips/translate.c | 378 
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 378 insertions(+)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 8c33d14..9c8d1f4 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -17202,6 +17202,380 @@ static void 
> gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
>      tcg_temp_free(v0_t);
>  }
> 


> +        case NM_MADDU:
> +            {
> +                int acc = extract32(ctx->opcode, 14, 2);
> +
> +                TCGv_i64 t2 = tcg_temp_new_i64();
> +                TCGv_i64 t3 = tcg_temp_new_i64();
> +
> +                gen_load_gpr(t0, rs);
> +                gen_load_gpr(t1, rt);
> +
> +                check_dsp(ctx);
> +                tcg_gen_ext32u_tl(t0, t0);
> +                tcg_gen_ext32u_tl(t1, t1);
> +                tcg_gen_extu_tl_i64(t2, t0);
> +                tcg_gen_extu_tl_i64(t3, t1);
> +                tcg_gen_mul_i64(t2, t2, t3);
> +                tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
> +                tcg_gen_add_i64(t2, t2, t3);
> +                tcg_temp_free_i64(t3);
> +                gen_move_low32(cpu_LO[acc], t2);
> +                gen_move_high32(cpu_HI[acc], t2);
> +                tcg_temp_free_i64(t2);
> +            }
> +            break;
 
check_dsp() should be as early as possible in this and other similar code 
segments.
 
> +        case NM_MULTU:
> +            {
> +                int acc = extract32(ctx->opcode, 14, 2);
> +
> +                TCGv_i32 t2 = tcg_temp_new_i32();
> +                TCGv_i32 t3 = tcg_temp_new_i32();
> +
> +                gen_load_gpr(t0, rs);
> +                gen_load_gpr(t1, rt);
> +
> +                check_dsp(ctx);
> +                tcg_gen_trunc_tl_i32(t2, t0);
> +                tcg_gen_trunc_tl_i32(t3, t1);
> +                tcg_gen_mulu2_i32(t2, t3, t2, t3);
> +                tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
> +                tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
> +                tcg_temp_free_i32(t2);
> +                tcg_temp_free_i32(t3);
> +            }
> +            break;
 
 Same.
 
> +        case NM_MSUB:
> +            {
> +                int acc = extract32(ctx->opcode, 14, 2);
> +
> +                TCGv_i64 t2 = tcg_temp_new_i64();
> +                TCGv_i64 t3 = tcg_temp_new_i64();
> +
> +                gen_load_gpr(t0, rs);
> +                gen_load_gpr(t1, rt);
> +
> +                check_dsp(ctx);
> +                tcg_gen_ext_tl_i64(t2, t0);
> +                tcg_gen_ext_tl_i64(t3, t1);
> +                tcg_gen_mul_i64(t2, t2, t3);
> +                tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
> +                tcg_gen_sub_i64(t2, t3, t2);
> +                tcg_temp_free_i64(t3);
> +                gen_move_low32(cpu_LO[acc], t2);
> +                gen_move_high32(cpu_HI[acc], t2);
> +                tcg_temp_free_i64(t2);
> +            }
> +            break;
 
 Same.
 
> +        case NM_MSUBU:
> +            {
> +                int acc = extract32(ctx->opcode, 14, 2);
> +
> +                TCGv_i64 t2 = tcg_temp_new_i64();
> +                TCGv_i64 t3 = tcg_temp_new_i64();
> +
> +                gen_load_gpr(t0, rs);
> +                gen_load_gpr(t1, rt);
> +
> +                check_dsp(ctx);
> +                tcg_gen_ext32u_tl(t0, t0);
> +                tcg_gen_ext32u_tl(t1, t1);
> +                tcg_gen_extu_tl_i64(t2, t0);
> +                tcg_gen_extu_tl_i64(t3, t1);
> +                tcg_gen_mul_i64(t2, t2, t3);
> +                tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
> +                tcg_gen_sub_i64(t2, t3, t2);
> +                tcg_temp_free_i64(t3);
> +                gen_move_low32(cpu_LO[acc], t2);
> +                gen_move_high32(cpu_HI[acc], t2);
> +                tcg_temp_free_i64(t2);
> +            }
> +            break;
 
 Same.