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[Qemu-devel] [PULL 01/45] target/arm: Forbid unprivileged mode for M Bas
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/45] target/arm: Forbid unprivileged mode for M Baseline |
Date: |
Tue, 14 Aug 2018 19:17:31 +0100 |
From: Julia Suvorova <address@hidden>
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 66afb08ee0f..a6d642f4ae5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10728,8 +10728,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t
maskreg, uint32_t val)
write_v7m_control_spsel_for_secstate(env,
val &
R_V7M_CONTROL_SPSEL_MASK,
M_REG_NS);
- env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
- env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
+ if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
+ env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
+ }
return;
case 0x98: /* SP_NS */
{
@@ -10822,8 +10824,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t
maskreg, uint32_t val)
!arm_v7m_is_handler_mode(env)) {
write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) !=
0);
}
- env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
- env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
+ if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
+ env->v7m.control[env->v7m.secure] |= val &
R_V7M_CONTROL_NPRIV_MASK;
+ }
break;
default:
bad_reg:
--
2.18.0
- [Qemu-devel] [PULL 00/45] target-arm queue, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 04/45] nvic: Change NVIC to support ARMv6-M, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 06/45] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 08/45] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 03/45] arm: Add ARMv6-M programmer's model support, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 01/45] target/arm: Forbid unprivileged mode for M Baseline,
Peter Maydell <=
- [Qemu-devel] [PULL 14/45] intc/arm_gic: Remove some dead code and put some functions static, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 07/45] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 11/45] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 16/45] intc/arm_gic: Add the virtualization extensions to the GIC state, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 28/45] intc/arm_gic: Implement maintenance interrupt generation, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 15/45] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 36/45] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 10/45] target/arm: Allow execution from small regions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 12/45] intc/arm_gic: Refactor operations on the distributor, Peter Maydell, 2018/08/14