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[Qemu-devel] [PULL 34/45] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TD
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 34/45] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks |
Date: |
Tue, 14 Aug 2018 19:18:04 +0100 |
Some debug registers can be trapped via MDCR_EL2 bits TDRA, TDOSA,
and TDA, which we implement in the functions access_tdra(),
access_tdosa() and access_tda(). If MDCR_EL2.TDE or HCR_EL2.TGE
are 1, the TDRA, TDOSA and TDA bits should behave as if they were 1.
Implement this by having the access functions check MDCR_EL2.TDE
and HCR_EL2.TGE.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 02c1c4d8404..3cd43cf7018 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -444,9 +444,11 @@ static CPAccessResult access_tdosa(CPUARMState *env, const
ARMCPRegInfo *ri,
bool isread)
{
int el = arm_current_el(env);
+ bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) ||
+ (env->cp15.mdcr_el2 & MDCR_TDE) ||
+ (env->cp15.hcr_el2 & HCR_TGE);
- if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
- && !arm_is_secure_below_el3(env)) {
+ if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) {
return CP_ACCESS_TRAP_EL2;
}
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
@@ -462,9 +464,11 @@ static CPAccessResult access_tdra(CPUARMState *env, const
ARMCPRegInfo *ri,
bool isread)
{
int el = arm_current_el(env);
+ bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) ||
+ (env->cp15.mdcr_el2 & MDCR_TDE) ||
+ (env->cp15.hcr_el2 & HCR_TGE);
- if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
- && !arm_is_secure_below_el3(env)) {
+ if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) {
return CP_ACCESS_TRAP_EL2;
}
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
@@ -480,9 +484,11 @@ static CPAccessResult access_tda(CPUARMState *env, const
ARMCPRegInfo *ri,
bool isread)
{
int el = arm_current_el(env);
+ bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) ||
+ (env->cp15.mdcr_el2 & MDCR_TDE) ||
+ (env->cp15.hcr_el2 & HCR_TGE);
- if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA)
- && !arm_is_secure_below_el3(env)) {
+ if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) {
return CP_ACCESS_TRAP_EL2;
}
if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
--
2.18.0
- [Qemu-devel] [PULL 35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions, (continued)
- [Qemu-devel] [PULL 35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 36/45] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 10/45] target/arm: Allow execution from small regions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 12/45] intc/arm_gic: Refactor operations on the distributor, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 13/45] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 22/45] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 19/45] intc/arm_gic: Refactor secure/ns access check in the CPU interface, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 24/45] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 31/45] arm/virt: Add support for GICv2 virtualization extensions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 32/45] arm: Fix return code of arm_load_elf, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 34/45] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks,
Peter Maydell <=
- [Qemu-devel] [PULL 38/45] target/arm: Improve exception-taken logging, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 39/45] target/arm: Initialize exc_secure correctly in do_v7m_exception_exit(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 41/45] target/arm: Implement tailchaining for M profile cores, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 45/45] target/arm: Fix typo in helper_sve_movz_d, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 20/45] intc/arm_gic: Add virtualization enabled IRQ helper functions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 21/45] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 42/45] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 27/45] intc/arm_gic: Implement gic_update_virt() function, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 44/45] target/arm: Reorganize SVE WHILE, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 05/45] accel/tcg: Pass read access type through to io_readx(), Peter Maydell, 2018/08/14