[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 03/30] target/arm: Fix offset for LD1R instructions
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/30] target/arm: Fix offset for LD1R instructions |
Date: |
Thu, 16 Aug 2018 14:34:11 +0100 |
From: Richard Henderson <address@hidden>
The immediate should be scaled by the size of the memory reference,
not the size of the elements into which it is loaded.
Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9e63b5f8e55..f635822a613 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4819,6 +4819,7 @@ static bool trans_LD1R_zpri(DisasContext *s,
arg_rpri_load *a, uint32_t insn)
unsigned vsz = vec_full_reg_size(s);
unsigned psz = pred_full_reg_size(s);
unsigned esz = dtype_esz[a->dtype];
+ unsigned msz = dtype_msz(a->dtype);
TCGLabel *over = gen_new_label();
TCGv_i64 temp;
@@ -4842,7 +4843,7 @@ static bool trans_LD1R_zpri(DisasContext *s,
arg_rpri_load *a, uint32_t insn)
/* Load the data. */
temp = tcg_temp_new_i64();
- tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);
+ tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
s->be_data | dtype_mop[a->dtype]);
--
2.18.0
- [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 06/30] target/arm: Dump SVE state if enabled, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 05/30] target/arm: Reformat integer register dump, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 07/30] target/arm: Add sve-max-vq cpu property to -cpu max, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 04/30] target/arm: Fix offset scaling for LD_zprr and ST_zprr, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 10/30] i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 02/30] target/arm: Fix sign-extension in sve do_ldr/do_str, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 03/30] target/arm: Fix offset for LD1R instructions,
Peter Maydell <=
- [Qemu-devel] [PULL 08/30] i.MX6UL: Add i.MX6UL specific CCM device, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 11/30] hw/arm: make bitbanded IO optional on ARMv7-M, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 13/30] loader: extract rom_free() function, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 14/30] loader: add rom transaction API, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 16/30] Add QTest testcase for the Intel Hexadecimal, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 20/30] aspeed_sdmc: Set 'cache initial sequence' always true, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 21/30] aspeed_sdmc: Init status always idle, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 12/30] target/arm: add "cortex-m0" CPU model, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 01/30] target/arm: Fix typo in helper_sve_ld1hss_r, Peter Maydell, 2018/08/16