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[Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interr
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts |
Date: |
Thu, 16 Aug 2018 09:11:46 -0700 |
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis <address@hidden>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbf..7cb2742070 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,7 +45,7 @@ enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
- VIRTIO_NDEV = 10
+ VIRTIO_NDEV = 0x35
};
enum {
--
2.17.1
- [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts,
Alistair Francis <=
- [Qemu-devel] [PATCH v3 3/6] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/08/16