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[Qemu-devel] [PULL v2 08/15] target/mips: Implement CP0 Config1.WR bit f
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 08/15] target/mips: Implement CP0 Config1.WR bit functionality |
Date: |
Thu, 16 Aug 2018 19:49:00 +0200 |
From: Stefan Markovic <address@hidden>
Add testing Config1.WR bit into watch exception handling logic.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ae3aaab..395368b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5521,6 +5521,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -5538,6 +5539,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6220,6 +6222,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6237,6 +6240,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6923,6 +6927,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6940,6 +6945,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7604,6 +7610,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7621,6 +7628,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
--
2.7.4
- [Qemu-devel] [PULL v2 00/15] MIPS queue for QEMU upstream, August 16, 2018, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 01/15] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 02/15] target/mips: Avoid case statements formulated by ranges - part 1, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 03/15] target/mips: Avoid case statements formulated by ranges - part 2, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 04/15] target/mips: Mark switch fallthroughs with interpretable comments, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 05/15] target/mips: Fix two instances of shadow variables, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 06/15] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 07/15] target/mips: Add CP0 BadInstrX register, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 08/15] target/mips: Implement CP0 Config1.WR bit functionality,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 09/15] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 11/15] elf: Remove duplicate preprocessor constant definition, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 10/15] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 12/15] elf: Add ELF flags for MIPS machine variants, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 14/15] linux-user: Add preprocessor availability control to some syscalls, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 13/15] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 15/15] qemu-doc: Amend MIPS-related items, Aleksandar Markovic, 2018/08/16
- Re: [Qemu-devel] [PULL v2 00/15] MIPS queue for QEMU upstream, August 16, 2018, Peter Maydell, 2018/08/17