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[Qemu-devel] [PULL v3 34/46] target/mips: Add emulation of DSP ASE for n
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v3 34/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6 |
Date: |
Tue, 21 Aug 2018 15:31:44 +0200 |
From: Stefan Markovic <address@hidden>
Add emulation of DSP ASE instructions for nanoMIPS - part 6.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5575964..89ccb95 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17911,6 +17911,60 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext
*ctx, uint32_t opc,
tcg_temp_free(t0);
}
+static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
+ int rt, int rs, int rd)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv rs_t = tcg_temp_new();
+
+ gen_load_gpr(rs_t, rs);
+
+ switch (opc) {
+ case NM_SHRA_R_QB:
+ check_dspr2(ctx);
+ tcg_gen_movi_tl(t0, rd >> 2);
+ switch (extract32(ctx->opcode, 12, 1)) {
+ case 0:
+ /* NM_SHRA_QB */
+ gen_helper_shra_qb(t0, t0, rs_t);
+ gen_store_gpr(t0, rt);
+ break;
+ case 1:
+ /* NM_SHRA_R_QB */
+ gen_helper_shra_r_qb(t0, t0, rs_t);
+ gen_store_gpr(t0, rt);
+ break;
+ }
+ break;
+ case NM_SHRL_PH:
+ check_dspr2(ctx);
+ tcg_gen_movi_tl(t0, rd >> 1);
+ gen_helper_shrl_ph(t0, t0, rs_t);
+ gen_store_gpr(t0, rt);
+ break;
+ case NM_REPL_QB:
+ check_dsp(ctx);
+ {
+ int16_t imm;
+ target_long result;
+ imm = extract32(ctx->opcode, 13, 8);
+ result = (uint32_t)imm << 24 |
+ (uint32_t)imm << 16 |
+ (uint32_t)imm << 8 |
+ (uint32_t)imm;
+ result = (int32_t)result;
+ tcg_gen_movi_tl(t0, result);
+ gen_store_gpr(t0, rt);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(rs_t);
+}
+
static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
@@ -18006,6 +18060,10 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState
*env, DisasContext *ctx)
}
break;
case NM_POOL32AXF_7:
+ {
+ int32_t op1 = extract32(ctx->opcode, 9, 3);
+ gen_pool32axf_7_nanomips_insn(ctx, op1, rt, rs, rd);
+ }
break;
default:
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
- [Qemu-devel] [PULL v3 00/46] MIPS queue August 21, 2018 v3, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 06/46] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 13/46] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 09/46] target/mips: Add emulation of nanoMIPS 16-bit shift instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 02/46] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 04/46] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 14/46] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 34/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v3 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 01/46] target/mips: Add preprocessor constants for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 15/46] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 27/46] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 20/46] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 33/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 31/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 28/46] target/mips: Implement MT ASE support for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL v3 07/46] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Aleksandar Markovic, 2018/08/21