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[Qemu-devel] [PATCH v4 1/9] target/mips: Introduce MXU registers
From: |
Craig Janeczek |
Subject: |
[Qemu-devel] [PATCH v4 1/9] target/mips: Introduce MXU registers |
Date: |
Thu, 30 Aug 2018 15:30:11 -0400 |
Define and initialize the 16 MXU registers.
Signed-off-by: Craig Janeczek <address@hidden>
---
v1
- NA
v2
- NA
v3
- Initial patch, split out from prior first patch
v4
- fixed reg name alignment
- added braces around init for loop
- Split mxu_CR out of the mxu_gpr array
target/mips/cpu.h | 2 ++
target/mips/translate.c | 20 ++++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 009202cf64..ff356f529b 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -170,6 +170,8 @@ struct TCState {
MSACSR_FS_MASK)
float_status msa_fp_status;
+ target_ulong mxu_gpr[15];
+ target_ulong mxu_cr;
};
typedef struct CPUMIPSState CPUMIPSState;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bdd880bb77..19b90c8735 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1398,6 +1398,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
+/* MXU registers */
+static TCGv mxu_gpr[15];
+static TCGv mxu_CR;
+
#include "exec/gen-icount.h"
#define gen_helper_0e0i(name, arg) do { \
@@ -1517,6 +1521,11 @@ static const char * const msaregnames[] = {
"w30.d0", "w30.d1", "w31.d0", "w31.d1",
};
+static const char * const mxuregnames[] = {
+ "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
+ "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "XR16",
+};
+
#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
@@ -20742,6 +20751,17 @@ void mips_tcg_init(void)
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState,
active_fpu.fcr31),
"fcr31");
+
+ for (i = 0; i < 15; i++) {
+ mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState,
+ active_tc.mxu_gpr[i]),
+ mxuregnames[i]);
+ }
+
+ mxu_CR = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState, active_tc.mxu_cr),
+ "MXU_CR");
}
#include "translate_init.inc.c"
--
2.18.0
- [Qemu-devel] [PATCH v4 0/9] Add limited MXU instruction support, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 3/9] target/mips: Split mips instruction handling, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 4/9] target/mips: Add MXU instructions S32I2M and S32M2I, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and S32LDDR, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 2/9] target/mips: Add all MXU opcodes, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 1/9] target/mips: Introduce MXU registers,
Craig Janeczek <=
- [Qemu-devel] [PATCH v4 8/9] target/mips: Add MXU instructions Q8MUL and Q8MULSU, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 6/9] target/mips: Add MXU instruction D16MUL, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 7/9] target/mips: Add MXU instruction D16MAC, Craig Janeczek, 2018/08/30
- [Qemu-devel] [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD, Craig Janeczek, 2018/08/30