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[Qemu-devel] [PULL v2 01/10] RISC-V: Update address bits to support sv39
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PULL v2 01/10] RISC-V: Update address bits to support sv39 and sv48 |
Date: |
Wed, 5 Sep 2018 15:09:24 -0700 |
From: Michael Clark <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34abc383e3..e0608e6d5f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,12 +24,12 @@
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
#if defined(TARGET_RISCV64)
#define TARGET_LONG_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 50
-#define TARGET_VIRT_ADDR_SPACE_BITS 39
+#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
+#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#elif defined(TARGET_RISCV32)
#define TARGET_LONG_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 34
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
+#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TCG_GUEST_DEFAULT_MO 0
--
2.17.1
- [Qemu-devel] [PULL v2 00/10] riscv-pullreq queue, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 01/10] RISC-V: Update address bits to support sv39 and sv48,
Alistair Francis <=
- [Qemu-devel] [PULL v2 02/10] RISC-V: Improve page table walker spec compliance, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 03/10] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 09/10] hw/riscv/spike: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 05/10] target/riscv: optimize cross-page direct jumps in softmmu, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 04/10] RISC-V: Simplify riscv_cpu_local_irqs_pending, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 07/10] target/riscv: call gen_goto_tb on DISAS_TOO_MANY, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 06/10] target/riscv: optimize indirect branches, Alistair Francis, 2018/09/05
- [Qemu-devel] [PULL v2 08/10] hw/riscv/virtio: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/09/05
- Re: [Qemu-devel] [PULL v2 00/10] riscv-pullreq queue, Peter Maydell, 2018/09/24