Re: [Qemu-devel] [PATCH 07/11] aspeed/smc: add a 'sdram_base' and 'max-ram-size' properties

[Cédric Le Goater]

On 09/18/2018 08:47 PM, Peter Maydell wrote:
> On 31 August 2018 at 11:38, Cédric Le Goater <address@hidden> wrote:
>> The setting of the DRAM address of the DMA transaction depends on the
>> DRAM base address and the maximun DRAM size of the SoC. Let's add a
>> couple of properties to give this information to the SMC controller
>> model.
> 
> In hardware, does the SMC controller really know the base address
> of DRAM,
Here is the definition of the DMA DRAM Side Address register

On the AST2500 : 
        
        31:30    reserved 0x2
        29:2     DRAM side start address. Only 4 bytes boundary.
                 The valid range is 0x80000000-0xBFFFFFFF
        1:0      reserved

On the AST2400 :

        31:29    reserved 0x2
        28:2     DRAM side start address. Only 4 bytes boundary. 
                 The valid range is 0x40000000-0x5FFFFFFF
        1:0      reserved

The DRAM address ranges are hardwired to fit the DRAM base address 
of the SoC and its maximum size, depending on the revision. Same 
for the flash address. The value just wraps around when the maximum 
is reached. 

> or is it actually emitting transactions that the bus fabric in 
> the SoC sends to the right place? 

The address is limited by the register definition before sending the 
transaction AFAICT. 

> That is, would
> it be more accurate to model it by passing the SMC controller a
> MemoryRegion to use for emitting DMA transactions which was an
> alias into the right part of the address space ?

I think you already proposed that a while ago. That would mean adding 
an address space and a memory region acting as a translating proxy. 

OK. I will look into it.

Thanks,

C.