qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU


From: Philippe Mathieu-Daudé
Subject: Re: [Qemu-devel] [PATCH v5 6/8] target/mips: Define the R5900 CPU
Date: Fri, 21 Sep 2018 00:39:45 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0

Hi Fredrik,

On 9/15/18 11:50 AM, Fredrik Noring wrote:
> The primary purpose of this change is to support programs compiled by
> GCC for the R5900 target and thereby run R5900 Linux distributions, for
> example Gentoo. In particular, this avoids issues with cross compilation.
> 
> This change has been tested with Gentoo compiled for R5900, including
> native compilation of several packages under QEMU.
> 
> Signed-off-by: Fredrik Noring <address@hidden>
> ---
>  target/mips/translate_init.inc.c | 47 
> ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/target/mips/translate_init.inc.c 
> b/target/mips/translate_init.inc.c
> index b3320b9dc7..71fd83de06 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -410,6 +410,53 @@ const mips_def_t mips_defs[] =
>          .insn_flags = CPU_MIPS32R5 | ASE_MSA,
>          .mmu_type = MMU_TYPE_R4000,
>      },
> +    {
> +        .name = "R5900",

What bothers me here is you are not modeling "The" unique R5900, but a
cpu which implements the R5900 architecture.

>From the "TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)":

  The TX7901 MIPS RISC microcontroller is a highly integrated solution
  based on Toshiba’s dual-issue super-scalar pipeline Processor Core,
  the C790 (henceforth referred to as “the C790”).

  C790 High-performance MIPS CPU Core on which the TX7901 is based.

So the correct core name is "C790".

> +        .CP0_PRid = 0x00003800,

"The implementation number of the C790 processor is 0x38".

OK (note again the correct name: "C790").

> +        /* No L2 cache, icache size 32k, dcache size 32k, uncached 
> coherency. */
> +        .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),

>From the DS:

  The C790 core has the following features:
   - Large on-chip caches
    • Instruction cache: 32KB, 2-way set associative
    • Data cache: 32KB, 2-way set-associative (with write-back protocol)

0x2 << CP0C0_K0 is 'Uncached', why you selected this and not 0x3 for
'Cacheable, write-back, write allocate'?

> +        .CP0_Status_rw_bitmask = 0xF4C79C1F,

Correct.

> +#ifdef CONFIG_USER_ONLY
> +        /*
> +         * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and 
> LL/SC
> +         * emulation. For user only, QEMU is the kernel, so we emulate the 
> traps
> +         * by simply emulating the instructions directly.
> +         *
> +         * Note: Config1 is only used internally, the R5900 has only Config0.
> +         */
> +        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),

Richard Henderson suggested to use ...:

           .CP0_Config1 = CP0C1_FP_USER_ONLY | (47 << CP0C1_MMU),

> +        .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
> +        .CP0_LLAddr_shift = 4,

... and Maciej said "No LL/SC in the R5900, so the LLAddr settings
 can go"; but you previously explained "kernel traps FPU instructions to
emulate them". That was clearer to me than "For user only, QEMU is the
kernel", but it is understandable.

> +        .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),

OK.

> +        .CP1_fcr31 = 0,
> +        .CP1_fcr31_rw_bitmask = 0x0183FFFF,

OK.

> +#else
> +        /*
> +         * The R5900 COP1 FPU implements single-precision floating-point
> +         * operations but is not entirely IEEE 754-1985 compatible. In
> +         * particular,
> +         *
> +         * - NaN (not a number) and plus/minus infinities are not supported;
> +         * - exception mechanisms are not fully supported;
> +         * - denormalized numbers are not supported;
> +         * - rounding towards nearest and plus/minus infinities are not 
> supported;
> +         * - computed results usually differs in the least significant bit;
> +         * - saturating instructions can differ more than the least 
> significant bit.
> +         *
> +         * Since only rounding towards zero is supported, the two least
> +         * significant bits of FCR31 are hardwired to 01.
> +         *
> +         * FPU emulation is disabled here until it is implemented.
> +         *
> +         * Note: Config1 is only used internally, the R5900 has only Config0.
> +         */
> +        .CP0_Config1 = (47 << CP0C1_MMU),

48 entry TLB, OK.

> +#endif /* !CONFIG_USER_ONLY */
> +        .SEGBITS = 32,

OK.

> +        .PABITS = 32,

20 bits PFN + 12 bits offset = 32 (Maciej, can you verify please?).

> +        .insn_flags = CPU_R5900,

I'd rather use:

           .insn_flags = CPU_MIPS3 | INSN_R5900,

But that's OK.

> +        .mmu_type = MMU_TYPE_R4000,

"The C790 processor provides a memory management unit
(MMU) [...] as the one implemented in R4000"

OK.

> +    },
>      {
>          /* A generic CPU supporting MIPS32 Release 6 ISA.
>             FIXME: Support IEEE 754-2008 FP.
> 

Regards,

Phil.



reply via email to

[Prev in Thread] Current Thread [Next in Thread]