Re: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU

[Philippe Mathieu-Daudé]

On 9/30/18 8:43 PM, Maciej W. Rozycki wrote:
> On Sun, 30 Sep 2018, Philippe Mathieu-Daudé wrote:
> 
>>>> I'd use:
>>>>
>>>>            MIPS_INVAL("mul/div Toshiba");
>>>
>>>  But just like `gen_mul_vr54xx' this function doesn't handle division!
>>
>> Per the commit message, I understood this function would eventually
>> handle "the R5900 specific pipeline 1 instruction variants MULT1,
>> MULTU1, DIV1, DIVU1, ..."
> 
>  Toshiba division instructions do not support the extra operand and always 
> return their result in the MD accumulator only.  The same applies to the 
> pipeline 1 instruction variants, so I've been thinking that a different 
> handler would better be used for DIV1 and DIVU1.  But maybe we can fold it 
> together after all and just force `rd' to be 0 at the call site for 
> DIV1/DIVU1.
> 
>  I'm not sure at this point which approach would be most beneficial, but 
> as it stands the function does not handle division operations.  If it 
> starts in the future, then we can rename/update it accordingly.

OK, so I think both agree to name this gen_mul_txx9().

>  Note that while the R5900 (shouldn't that be called TX59 actually?) or 

I also think of the R5900 as the TX59 member of the Toshiba TX family
but I never read the TX59 name, I suppose this is where Sony comes into
the game.

> TX79 do not implement DMULT or DMULTU, the Tx49 does and they do support 
> the extra `rd' operand there[1].  Still no DMADD or DMADDU though.

As does the TX39.

There is also the TX99 series (based on 25Kf):
https://www.toshiba.co.jp/about/press/2002_02/pr1901.htm

> References:
> 
> [1] "64-Bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture", 
>     Rev 1.0, Toshiba Corporation, September 2004, Table 5-8 "Extensions to 
>     the ISA: Multiply and Divide Instructions", p. 5-7
> 
>   Maciej
>