Re: [Qemu-devel] [PATCH v2 04/15] target/arm: Handle SVE vector length changes in system mode

[Peter Maydell]

On 26 September 2018 at 20:23, Richard Henderson
<address@hidden> wrote:
> SVE vector length can change when changing EL, or when writing
> to one of the ZCR_ELn registers.
>
> For correctness, our implementation requires that predicate bits
> that are inaccessible are never set.  Which means noticing length
> changes and zeroing the appropriate register bits.
>
> Tested-by: Laurent Desnogues <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>

> +
> +/*
> + * Notice a change in SVE vector size when changing EL.
> + */
> +void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el)
> +{
> +    int old_len, new_len;
> +
> +    /* Nothing to do if no SVE.  */
> +    if (!arm_feature(env, ARM_FEATURE_SVE)) {
> +        return;
> +    }
> +
> +    /* Nothing to do if FP is disabled in either EL.  */
> +    if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
> +        return;
> +    }
> +
> +    /*
> +     * When FP is enabled, but SVE is disabled, the effective len is 0.
> +     * ??? Do we need a conditional for old_el/new_el in aa32 state?
> +     * That isn't included in the CheckSVEEnabled pseudocode, so is the
> +     * host kernel required to explicitly disable SVE for an EL using aa32?
> +     */

Possibly relevant here is DDI0584A.d section 3.2 (that's the
SVE Arm ARM supplement), which says "If SVE instructions are
disabled or trapped at ELx, or not available because that Exception
level is in AArch32 state, then for all purposes other than a direct
read, the ZCR_ELx.LEN field has an Effective value of 0".

My assumption is that the CheckSVEEnabled pseudacode doesn't look
for the exception level being AArch32 because it's not possible
to reach that function in AArch32 mode.

thanks
-- PMM