[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 09/33] target/arm: Adjust aarch64_cpu_dump_state for
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/33] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE |
Date: |
Mon, 8 Oct 2018 14:59:40 +0100 |
From: Richard Henderson <address@hidden>
Use the existing helpers to determine if (1) the fpu is enabled,
(2) sve state is enabled, and (3) the current sve vector length.
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 4 ++++
target/arm/helper.c | 6 +++---
target/arm/translate-a64.c | 8 ++++++--
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a4ee83dc770..da4d3888eab 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -920,6 +920,10 @@ target_ulong do_arm_semihosting(CPUARMState *env);
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
+int fp_exception_el(CPUARMState *env, int cur_el);
+int sve_exception_el(CPUARMState *env, int cur_el);
+uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
+
static inline bool is_a64(CPUARMState *env)
{
return env->aarch64;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 72f7f5cfec2..efe42f9e079 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4406,7 +4406,7 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
* take care of raising that exception.
* C.f. the ARM pseudocode function CheckSVEEnabled.
*/
-static int sve_exception_el(CPUARMState *env, int el)
+int sve_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1) {
@@ -4464,7 +4464,7 @@ static int sve_exception_el(CPUARMState *env, int el)
/*
* Given that SVE is enabled, return the vector length for EL.
*/
-static uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
{
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t zcr_len = cpu->sve_max_vq - 1;
@@ -12546,7 +12546,7 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,
uint32_t bytes)
/* Return the exception level to which FP-disabled exceptions should
* be taken, or 0 if FP is enabled.
*/
-static int fp_exception_el(CPUARMState *env, int cur_el)
+int fp_exception_el(CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
int fpen;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8ca3876707c..8a24278d797 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -166,11 +166,15 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, "\n");
return;
}
+ if (fp_exception_el(env, el) != 0) {
+ cpu_fprintf(f, " FPU disabled\n");
+ return;
+ }
cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
vfp_get_fpcr(env), vfp_get_fpsr(env));
- if (arm_feature(env, ARM_FEATURE_SVE)) {
- int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */
+ if (arm_feature(env, ARM_FEATURE_SVE) && sve_exception_el(env, el) == 0) {
+ int j, zcr_len = sve_zcr_len_for_el(env, el);
for (i = 0; i <= FFR_PRED_NUM; i++) {
bool eol;
--
2.19.0
- [Qemu-devel] [PULL 12/33] target/arm: Rewrite helper_sve_ld[234]*_r, (continued)
- [Qemu-devel] [PULL 12/33] target/arm: Rewrite helper_sve_ld[234]*_r, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 14/33] target/arm: Split contiguous loads for endianness, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 16/33] target/arm: Rewrite vector gather loads, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 21/33] target/arm: Define new EXCP type for v8M stack overflows, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 20/33] target/arm: Define new TBFLAG for v8M stack checking, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 19/33] target/arm: Pass TCGMemOpIdx to sve memory helpers, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 17/33] target/arm: Rewrite vector gather stores, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 18/33] target/arm: Rewrite vector gather first-fault loads, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 22/33] target/arm: Move v7m_using_psp() to internals.h, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD1RQ, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 09/33] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE,
Peter Maydell <=
- [Qemu-devel] [PULL 23/33] target/arm: Add v8M stack checks on ADD/SUB/MOV of SP, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 08/33] target/arm: Handle SVE vector length changes in system mode, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 13/33] target/arm: Rewrite helper_sve_st[1234]*_r, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 32/33] target/arm: Add v8M stack checks for MSR to SP_NS, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 33/33] hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 31/33] target/arm: Add v8M stack checks for VLDM/VSTM, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 29/33] target/arm: Add v8M stack checks for T32 load/store single, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 30/33] target/arm: Add v8M stack checks for Thumb push/pop, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 24/33] target/arm: Add some comments in Thumb decode, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 25/33] target/arm: Add v8M stack checks on exception entry, Peter Maydell, 2018/10/08