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[Qemu-devel] [PATCH 01/20] target/arm: Hoist address increment for vecto
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 01/20] target/arm: Hoist address increment for vector memory ops |
Date: |
Thu, 11 Oct 2018 13:51:47 -0700 |
From: Richard Henderson <address@hidden>
This can reduce the number of opcodes required for certain
complex forms of load-multiple (e.g. ld4.16b).
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c403b12eb9..76b5ca3606 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3012,7 +3012,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
bool is_store = !extract32(insn, 22, 1);
bool is_postidx = extract32(insn, 23, 1);
bool is_q = extract32(insn, 30, 1);
- TCGv_i64 tcg_addr, tcg_rn;
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
int ebytes = 1 << size;
int elements = (is_q ? 128 : 64) / (8 << size);
@@ -3077,6 +3077,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
tcg_rn = cpu_reg_sp(s, rn);
tcg_addr = tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn);
+ tcg_ebytes = tcg_const_i64(ebytes);
for (r = 0; r < rpt; r++) {
int e;
@@ -3101,7 +3102,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
clear_vec_high(s, is_q, tt);
}
}
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
tt = (tt + 1) % 32;
}
}
@@ -3115,6 +3116,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
}
}
+ tcg_temp_free_i64(tcg_ebytes);
tcg_temp_free_i64(tcg_addr);
}
@@ -3157,7 +3159,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
bool replicate = false;
int index = is_q << 3 | S << 2 | size;
int ebytes, xs;
- TCGv_i64 tcg_addr, tcg_rn;
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
switch (scale) {
case 3:
@@ -3210,6 +3212,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
tcg_rn = cpu_reg_sp(s, rn);
tcg_addr = tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn);
+ tcg_ebytes = tcg_const_i64(ebytes);
for (xs = 0; xs < selem; xs++) {
if (replicate) {
@@ -3252,7 +3255,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
do_vec_st(s, rt, index, tcg_addr, scale);
}
}
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
rt = (rt + 1) % 32;
}
@@ -3264,6 +3267,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
}
}
+ tcg_temp_free_i64(tcg_ebytes);
tcg_temp_free_i64(tcg_addr);
}
--
2.17.1
- [Qemu-devel] [PATCH 00/20] target/arm: Convert some neon insns to gvec, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 01/20] target/arm: Hoist address increment for vector memory ops,
Richard Henderson <=
- [Qemu-devel] [PATCH 02/20] target/arm: Don't call tcg_clear_temp_count, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 09/20] target/arm: Use gvec for NEON_3R_VADD_VSUB insns, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 17/20] target/arm: Use gvec for NEON VLD all lanes, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 11/20] target/arm: Use gvec for NEON_3R_VMUL, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 18/20] target/arm: Reorg NEON VLD/VST all elements, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 05/20] target/arm: Mark some arrays const, Richard Henderson, 2018/10/11