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[Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_l
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load() |
Date: |
Fri, 12 Oct 2018 19:30:39 +0200 |
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as gen_load() did.
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 44 +++++++++++++++++--------
target/riscv/translate.c | 20 -----------
2 files changed, 30 insertions(+), 34 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 6097b82df4..873a5e8b53 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -131,46 +131,62 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a,
uint32_t insn)
return trans_branch(ctx, a, TCG_COND_GEU);
}
-static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn)
+static bool trans_load(DisasContext *ctx, arg_lb *a, int memop)
{
- gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_addi_tl(t0, t0, a->imm);
+
+ if (memop < 0) {
+ return false;
+ }
+
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
return true;
}
+
+static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn)
+{
+ return trans_load(ctx, a, MO_SB);
+}
+
static bool trans_lh(DisasContext *ctx, arg_lh *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm);
- return true;
+ return trans_load(ctx, a, MO_TESW);
}
+
static bool trans_lw(DisasContext *ctx, arg_lw *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm);
- return true;
+ return trans_load(ctx, a, MO_TESL);
}
+
static bool trans_lbu(DisasContext *ctx, arg_lbu *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm);
- return true;
+ return trans_load(ctx, a, MO_UB);
}
+
static bool trans_lhu(DisasContext *ctx, arg_lhu *a, uint32_t insn)
{
- gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm);
- return true;
+ return trans_load(ctx, a, MO_TEUW);
}
static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
- return true;
+ return trans_load(ctx, a, MO_TEUL);
#else
return false;
#endif
}
+
static bool trans_ld(DisasContext *ctx, arg_ld *a, uint32_t insn)
{
#ifdef TARGET_RISCV64
- gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
- return true;
+ return trans_load(ctx, a, MO_TEQ);
#else
return false;
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b8a9b1c64b..544e71a46c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -488,26 +488,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx,
int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_addi_tl(t0, t0, imm);
- int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
-
- if (memop < 0) {
- gen_exception_illegal(ctx);
- return;
- }
-
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
- gen_set_gpr(rd, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
--
2.19.1
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), (continued)
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/12