Re: [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn

[Richard Henderson]

On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
>  static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
>  {
> -    gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
> -    return true;
> +    return trans_arith(ctx, a, &tcg_gen_mul_tl);
>  }
>  static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn)
>  {
> -    gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
> -    return true;
> +    return trans_arith_w(ctx, a, &gen_div);
>  }
>  static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn)
>  {
> -    gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
> -    return true;
> +    return trans_arith_w(ctx, a, &gen_divu);
>  }
>  static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn)
>  {
> -    gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
> -    return true;
> +    return trans_arith_w(ctx, a, &gen_rem);
>  }
>  static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn)
>  {
> -    gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
> -    return true;
> +    return trans_arith_w(ctx, a, &gen_remu);
>  }

Missing TARGET_RISCV64 checks.


r~