Re: [Qemu-devel] [PATCH v7 1/7] target/mips: Define R5900 instructions and CPU preprocessor constants

[Philippe Mathieu-Daudé]

On Sat, Oct 13, 2018 at 1:10 PM Fredrik Noring <address@hidden> wrote:
>
> The R5900 implements the 64-bit MIPS III instruction set except DMULT,
> DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN,
> MOVZ and PREF are implemented. It has the R5900 specific three-operand
> instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions
> MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and
> MTLO1. A set of 93 128-bit multimedia instructions specific to the
> R5900 is also implemented.
>
> The Toshiba TX System RISC TX79 Core Architecture manual
>
> http://www.lukasz.dk/files/tx79architecture.pdf

Also available on https://wiki.qemu.org/File:C790.pdf

>
> describes the C790 processor that is a follow-up to the R5900. There
> are a few notable differences in that the R5900 FPU
>
> - is not IEEE 754-1985 compliant,
> - does not implement double format, and
> - its machine code is nonstandard.
>
> Signed-off-by: Fredrik Noring <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
>  target/mips/mips-defs.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
> index c8e99791ad..76550de2da 100644
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -53,6 +53,7 @@
>  #define   ASE_MSA       0x01000000
>
>  /* Chip specific instructions. */
> +#define         INSN_R5900       0x10000000
>  #define                INSN_LOONGSON2E  0x20000000
>  #define                INSN_LOONGSON2F  0x40000000
>  #define                INSN_VR54XX     0x80000000
> @@ -63,6 +64,7 @@
>  #define                CPU_MIPS3       (CPU_MIPS2 | ISA_MIPS3)
>  #define                CPU_MIPS4       (CPU_MIPS3 | ISA_MIPS4)
>  #define                CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)
> +#define         CPU_R5900       (CPU_MIPS3 | INSN_R5900)
>  #define                CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
>  #define                CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)
>
> --
> 2.16.4
>