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[Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO |
Date: |
Tue, 16 Oct 2018 16:23:22 +0100 |
From: Aaron Lindsay <address@hidden>
I previously fixed this for PMINTENSET_EL1, but missed these.
Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0efbb5c76ce..138a1f15405 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1423,12 +1423,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.writefn = pmintenset_write, .raw_writefn = raw_write,
.resetvalue = 0x0 },
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 =
2,
- .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
+ .access = PL1_RW, .accessfn = access_tpm,
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.writefn = pmintenclr_write, },
{ .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
- .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
+ .access = PL1_RW, .accessfn = access_tpm,
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.writefn = pmintenclr_write },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
--
2.19.0
- [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers, (continued)
- [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of descriptor words, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO,
Peter Maydell <=
- [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 13/19] net: cadence_gem: Announce 64bit addressing support, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 15/19] target/arm: Add the Cortex-A72, Peter Maydell, 2018/10/16