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[Qemu-devel] [PATCH v5 08/14] target/mips: Add emulation of non-MXU MULL
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 08/14] target/mips: Add emulation of non-MXU MULL within MXU decoding engine |
Date: |
Fri, 19 Oct 2018 18:33:42 +0200 |
From: Craig Janeczek <address@hidden>
Add emulation of non-MXU MULL within MXU decoding engine.
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5b7e6f3..191aeab 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1654,7 +1654,7 @@ enum {
enum {
OPC_MXU_S32MADD = 0x00,
OPC_MXU_S32MADDU = 0x01,
- /* not assigned 0x02 */
+ OPC__MXU_MUL = 0x02,
OPC_MXU__POOL00 = 0x03,
OPC_MXU_S32MSUB = 0x04,
OPC_MXU_S32MSUBU = 0x05,
@@ -24276,6 +24276,18 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S32MADDU");
generate_exception_end(ctx, EXCP_RI);
break;
+ case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
+ {
+ uint32_t rs, rt, rd, op1;
+
+ rs = extract32(ctx->opcode, 21, 5);
+ rt = extract32(ctx->opcode, 16, 5);
+ rd = extract32(ctx->opcode, 11, 5);
+ op1 = MASK_SPECIAL2(ctx->opcode);
+
+ gen_arith(ctx, op1, rd, rs, rt);
+ }
+ break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
break;
--
2.7.4
- [Qemu-devel] [PATCH v5 00/14] Add limited MXU instruction support, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 01/14] target/mips: Introduce MXU registers, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 02/14] target/mips: Define a bit for MXU in insn_flags, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 03/14] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 04/14] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 05/14] target/mips: Add bit encoding for MXU add/subtract patterns 'aptn2', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 08/14] target/mips: Add emulation of non-MXU MULL within MXU decoding engine,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 14/14] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 07/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn3', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 06/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn2', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 10/14] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 11/14] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 09/14] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 12/14] target/mips: Add emulation of MXU instruction D16MAC, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 13/14] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/19