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From: | Richard Henderson |
Subject: | Re: [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree |
Date: | Tue, 23 Oct 2018 09:31:23 +0100 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/20/18 8:14 AM, Bastian Koppelmann wrote: > v1 -> v2: > - Stack allocate arg_c_* structs > - ex_rvc_register returns int > - special case of trans_c_addi4spn() returns false ... > +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a, > + uint16_t insn) > +{ > + if (a->nzuimm == 0) { > + /* Reserved in ISA */ > + gen_exception_illegal(ctx); > + return true; > + } That doesn't seem to have actually happened. But otherwise, Reviewed-by: Richard Henderson <address@hidden> r~
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