Re: [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND

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Re: [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND

From:	Richard Henderson
Subject:	Re: [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
Date:	Tue, 23 Oct 2018 09:53:27 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> +static bool trans_arith(DisasContext *ctx, arg_arith *a,
> +                        void(*func)(TCGv, TCGv, TCGv))

gen_arith.


r~

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[Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding, (continued)
- [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2018/10/20
  - Re: [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith, Richard Henderson, 2018/10/23
- [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/20
  - Re: [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Richard Henderson, 2018/10/23
  - Re: [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/24
- [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/20
  - Re: [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Richard Henderson <=
    - Re: [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Richard Henderson, 2018/10/23
- [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/20
  - Re: [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn, Richard Henderson, 2018/10/23
- Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree, Palmer Dabbelt, 2018/10/24
  - Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree, Bastian Koppelmann, 2018/10/26
    - Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree, Palmer Dabbelt, 2018/10/27

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