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[Qemu-devel] [PULL 09/28] x86_iommu/amd: remove V=1 check from amdvi_val
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL 09/28] x86_iommu/amd: remove V=1 check from amdvi_validate_dte() |
Date: |
Tue, 23 Oct 2018 19:41:31 -0400 |
From: "Singh, Brijesh" <address@hidden>
Currently, the amdvi_validate_dte() assumes that a valid DTE will
always have V=1. This is not true. The V=1 means that bit[127:1] are
valid. A valid DTE can have IV=1 and V=0 (i.e address translation
disabled and interrupt remapping enabled)
Remove the V=1 check from amdvi_validate_dte(), make the caller
responsible to check for V or IV bits.
This also fixes a bug in existing code that when error is
detected during the translation we'll fail the translation
instead of assuming a passthrough mode.
Signed-off-by: Brijesh Singh <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/amd_iommu.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 1fd669fef8..7206bb09c2 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -807,7 +807,7 @@ static inline uint64_t amdvi_get_perms(uint64_t entry)
AMDVI_DEV_PERM_SHIFT;
}
-/* a valid entry should have V = 1 and reserved bits honoured */
+/* validate that reserved bits are honoured */
static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid,
uint64_t *dte)
{
@@ -820,7 +820,7 @@ static bool amdvi_validate_dte(AMDVIState *s, uint16_t
devid,
return false;
}
- return dte[0] & AMDVI_DEV_VALID;
+ return true;
}
/* get a device table entry given the devid */
@@ -966,8 +966,12 @@ static void amdvi_do_translate(AMDVIAddressSpace *as,
hwaddr addr,
return;
}
- /* devices with V = 0 are not translated */
if (!amdvi_get_dte(s, devid, entry)) {
+ return;
+ }
+
+ /* devices with V = 0 are not translated */
+ if (!(entry[0] & AMDVI_DEV_VALID)) {
goto out;
}
--
MST
- [Qemu-devel] [PULL 00/28] pci, pc, virtio: fixes, features, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 04/28] intel_iommu: move ce fetching out when sync shadow, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 01/28] virtio-blk: fix comment for virtio_blk_rw_complete, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 05/28] intel_iommu: handle invalid ce for shadow sync, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 02/28] intel_iommu: introduce vtd_reset_caches(), Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 07/28] x86_iommu: move the kernel-irqchip check in common code, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 09/28] x86_iommu/amd: remove V=1 check from amdvi_validate_dte(),
Michael S. Tsirkin <=
- [Qemu-devel] [PULL 16/28] MAINTAINERS: list "tests/acpi-test-data" files in ACPI/SMBIOS section, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 06/28] vhost-user-blk: start vhost when guest kicks, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 17/28] pci-testdev: add optional memory bar, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 10/28] x86_iommu/amd: make the address space naming consistent with intel-iommu, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 24/28] pci_bridge: fix typo in comment, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 25/28] i440fx: use ARRAY_SIZE for pam_regions, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 08/28] x86_iommu: move vtd_generate_msi_message in common file, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 11/28] x86_iommu/amd: Prepare for interrupt remap support, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 19/28] hw/pci-host/x86: extend the 64-bit PCI hole relative to the fw-assigned base, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 03/28] intel_iommu: better handling of dmar state switch, Michael S. Tsirkin, 2018/10/23