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[Qemu-devel] [PULL v2 12/33] target/mips: Add a placeholder for R5900 MM
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 12/33] target/mips: Add a placeholder for R5900 MMI0 instruction subclass |
Date: |
Wed, 24 Oct 2018 15:40:26 +0200 |
From: Fredrik Noring <address@hidden>
Add a placeholder for MMI0 subclass.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6cb6966..1a9e43b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,15 +24420,56 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
}
}
+static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI0(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI0_PADDW: /* TODO: TX79_MMI0_PADDW */
+ case TX79_MMI0_PSUBW: /* TODO: TX79_MMI0_PSUBW */
+ case TX79_MMI0_PCGTW: /* TODO: TX79_MMI0_PCGTW */
+ case TX79_MMI0_PMAXW: /* TODO: TX79_MMI0_PMAXW */
+ case TX79_MMI0_PADDH: /* TODO: TX79_MMI0_PADDH */
+ case TX79_MMI0_PSUBH: /* TODO: TX79_MMI0_PSUBH */
+ case TX79_MMI0_PCGTH: /* TODO: TX79_MMI0_PCGTH */
+ case TX79_MMI0_PMAXH: /* TODO: TX79_MMI0_PMAXH */
+ case TX79_MMI0_PADDB: /* TODO: TX79_MMI0_PADDB */
+ case TX79_MMI0_PSUBB: /* TODO: TX79_MMI0_PSUBB */
+ case TX79_MMI0_PCGTB: /* TODO: TX79_MMI0_PCGTB */
+ case TX79_MMI0_PADDSW: /* TODO: TX79_MMI0_PADDSW */
+ case TX79_MMI0_PSUBSW: /* TODO: TX79_MMI0_PSUBSW */
+ case TX79_MMI0_PEXTLW: /* TODO: TX79_MMI0_PEXTLW */
+ case TX79_MMI0_PPACW: /* TODO: TX79_MMI0_PPACW */
+ case TX79_MMI0_PADDSH: /* TODO: TX79_MMI0_PADDSH */
+ case TX79_MMI0_PSUBSH: /* TODO: TX79_MMI0_PSUBSH */
+ case TX79_MMI0_PEXTLH: /* TODO: TX79_MMI0_PEXTLH */
+ case TX79_MMI0_PPACH: /* TODO: TX79_MMI0_PPACH */
+ case TX79_MMI0_PADDSB: /* TODO: TX79_MMI0_PADDSB */
+ case TX79_MMI0_PSUBSB: /* TODO: TX79_MMI0_PSUBSB */
+ case TX79_MMI0_PEXTLB: /* TODO: TX79_MMI0_PEXTLB */
+ case TX79_MMI0_PPACB: /* TODO: TX79_MMI0_PPACB */
+ case TX79_MMI0_PEXT5: /* TODO: TX79_MMI0_PEXT5 */
+ case TX79_MMI0_PPAC5: /* TODO: TX79_MMI0_PPAC5 */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI0 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI0");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
switch (opc) {
+ case TX79_MMI_CLASS_MMI0:
+ decode_tx79_mmi0(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_CLASS_MMI0: /* TODO: TX79_MMI_CLASS_MMI0 */
case TX79_MMI_CLASS_MMI2: /* TODO: TX79_MMI_CLASS_MMI2 */
case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
--
2.7.4
- [Qemu-devel] [PULL v2 02/33] target/mips: Add R5900 Multimedia Instruction overview note, (continued)
- [Qemu-devel] [PULL v2 02/33] target/mips: Add R5900 Multimedia Instruction overview note, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 13/33] target/mips: Add a placeholder for R5900 MMI1 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 09/33] target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 04/33] target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 03/33] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 11/33] target/mips: Add a placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 14/33] target/mips: Add a placeholder for R5900 MMI2 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 16/33] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 05/33] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 06/33] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 12/33] target/mips: Add a placeholder for R5900 MMI0 instruction subclass,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 08/33] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 20/33] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 29/33] tests/tcg/mips: Add tests for R5900 DIVU1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 24/33] tests/tcg/mips: Add tests for R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 17/33] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 23/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 18/33] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 30/33] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 26/33] tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 22/33] tests/tcg/mips: Add tests for R5900 three-operand MULT, Aleksandar Markovic, 2018/10/24