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Re: [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze |
Date: |
Thu, 25 Oct 2018 19:34:27 +0100 |
On 17 October 2018 at 22:54, Palmer Dabbelt <address@hidden> wrote:
> The following changes since commit 09558375a634e17cea6cfbfec883ac2376d2dc7f:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging (2018-10-16
> 17:42:56 +0100)
>
> are available in the Git repository at:
>
> git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-sf0
>
> for you to fetch changes up to 7c28f4da20e5585dce7d575691dac5392b7c6f78:
>
> RISC-V: Don't add NULL bootargs to device-tree (2018-10-17 13:02:30 -0700)
>
> ----------------------------------------------------------------
> First RISC-V Patch Set for the 3.1 Soft Freeze
>
> This pull request contains a handful of patches that have been floating
> around various trees for a while but haven't made it upstream. These
> patches all appear quite safe. They're all somewhat independent from
> each other:
>
> * One refactors our IRQ management function to allow multiple interrupts
> to be raised an once. This patch has no functional difference.
> * Cleaning up the op_helper/cpu_helper split. This patch has no
> functional difference.
> * Updates to various constants to keep them in sync with the latest ISA
> specification and to remove some non-standard bits that snuck in.
> * A fix for a memory leak in the PLIC driver.
> * A fix to our device tree handling to avoid provinging a NULL string.
>
> I've given this my standard test: building the port, booting a Fedora
> root filesytem on the latest Linux tag, and then shutting down that
> image. Essentially I'm just following the QEMU RISC-V wiki page's
> instructions. Everything looks fine here.
>
> We have a lot more outstanding patches so I'll definately be submitting
> another PR for the soft freeze.
>
> ----------------------------------------------------------------
Applied to master, thanks (following some off-list discussions
of what we are doing wrt who is submitting riscv upstream pullreqs).
-- PMM
- [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze, Palmer Dabbelt, 2018/10/17
- [Qemu-devel] [PULL 2/5] RISC-V: Move non-ops from op_helper to cpu_helper, Palmer Dabbelt, 2018/10/17
- [Qemu-devel] [PULL 1/5] RISC-V: Allow setting and clearing multiple irqs, Palmer Dabbelt, 2018/10/17
- [Qemu-devel] [PULL 5/5] RISC-V: Don't add NULL bootargs to device-tree, Palmer Dabbelt, 2018/10/17
- [Qemu-devel] [PULL 4/5] RISC-V: Add missing free for plic_hart_config, Palmer Dabbelt, 2018/10/17
- [Qemu-devel] [PULL 3/5] RISC-V: Update CSR and interrupt definitions, Palmer Dabbelt, 2018/10/17
- Re: [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze, Eric Blake, 2018/10/17
- Re: [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze,
Peter Maydell <=