Re: [Qemu-devel] [PATCH] target/arm: Conditionalize arm_div assert on aarch32 support

[Peter Maydell]

On 1 November 2018 at 21:57, Richard Henderson
<address@hidden> wrote:
> When populating id registers from kvm, on a host that doesn't support
> aarch32 mode at all, aa32_arm_div will not be supported either.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>
> "Tested" on an APM Mustang, which does support AArch32.  I'm not
> sure, off hand, which cpu(s) don't have it, and Alex didn't say
> in his bug report.  Tsk tsk.  ;-)
>
>
> r~
>
> ---
>  target/arm/cpu.h |  5 +++++
>  target/arm/cpu.c | 10 +++++++++-
>  2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 895f9909d8..4521ad5ae8 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3300,6 +3300,11 @@ static inline bool isar_feature_aa64_fp16(const 
> ARMISARegisters *id)
>      return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
>  }
>
> +static inline bool isar_feature_aa64_a32(const ARMISARegisters *id)
> +{
> +    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) == 2;
> +}
> +

Doesn't the stuff in the Arm ARM's "Principles of the ID
scheme for fields in ID registers" about signed and unsigned
values for ID register fields strictly mean you want to be
testing (unsigned) >= 2 here rather than strict equality?

thanks
-- PMM