[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 5/5] target/arm: Fix ATS1Hx instructions
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 5/5] target/arm: Fix ATS1Hx instructions |
Date: |
Tue, 6 Nov 2018 11:38:26 +0000 |
ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations
on the EL2 translation regime) were implemented in commit 14db7fe09a2c8.
However, we got them wrong: these should do stage 1 address translations
as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly
making them perform stage 2 translations.
A few years later in commit 1313e2d7e2cd we forgot entirely that
we'd implemented ATS1Hx, and added a comment that ATS1Hx were
"not supported yet". Remove the comment; there is no extra code
needed to handle these operations in do_ats_write(), because
arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
which forces 64-bit PAR format.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 69f684abd89..96301930cc8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2319,7 +2319,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
*
* (Note that HCR.DC makes HCR.VM behave as if it is 1.)
*
- * ATS1Hx always uses the 64bit format (not supported yet).
+ * ATS1Hx always uses the 64bit format.
*/
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
@@ -2444,7 +2444,7 @@ static void ats1h_write(CPUARMState *env, const
ARMCPRegInfo *ri,
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
- par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
--
2.19.1
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 2/5] milkymist: Check for failure trying to load BIOS image, Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 4/5] target/arm: Set S and PTW in 64-bit PAR format, Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 1/5] target/arm: Remove can't-happen if() from handle_vec_simd_shli(), Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 5/5] target/arm: Fix ATS1Hx instructions,
Peter Maydell <=
- [Qemu-devel] [PULL 3/5] hw/arm/exynos4210: Zero memory allocated for Exynos4210State, Peter Maydell, 2018/11/06
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2018/11/06