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Re: [Qemu-devel] [PATCH 1/2] target/riscv: Fix FCLASS_D being treated as
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH 1/2] target/riscv: Fix FCLASS_D being treated as RV64 only |
Date: |
Tue, 13 Nov 2018 12:06:36 -0800 |
On Thu, Nov 8, 2018 at 4:07 AM Bastian Koppelmann
<address@hidden> wrote:
>
> Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/riscv/translate.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 18d7b6d147..5359088e24 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1237,13 +1237,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t
> opc, int rd,
> tcg_temp_free(t0);
> break;
>
> -#if defined(TARGET_RISCV64)
> case OPC_RISC_FMV_X_D:
> /* also OPC_RISC_FCLASS_D */
> switch (rm) {
> +#if defined(TARGET_RISCV64)
> case 0: /* FMV */
> gen_set_gpr(rd, cpu_fpr[rs1]);
> break;
> +#endif
> case 1:
> t0 = tcg_temp_new();
> gen_helper_fclass_d(t0, cpu_fpr[rs1]);
> @@ -1255,6 +1256,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t
> opc, int rd,
> }
> break;
>
> +#if defined(TARGET_RISCV64)
> case OPC_RISC_FMV_D_X:
> t0 = tcg_temp_new();
> gen_get_gpr(t0, rs1);
> --
> 2.19.1
>
>