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[Qemu-devel] [RFC for-3.2 PATCH 6/7] pcie: Allow generic PCIe root port
From: |
Alex Williamson |
Subject: |
[Qemu-devel] [RFC for-3.2 PATCH 6/7] pcie: Allow generic PCIe root port to specify link speed and width |
Date: |
Wed, 14 Nov 2018 13:51:29 -0700 |
User-agent: |
StGit/0.18-136-gffd7-dirty |
Allow users to specify speed and width values for the generic PCIe
root port. Defaults remain at 2.5GT/s & x1 for compatiblity. Machine
based defaults to increase this, such as if we wanted a pc-q35-3.2
machine to default to 16GT/s & x32, can be triggered by implementing
an instance_init callback here.
Note for libvirt testing that pcie-root-port controllers are given
default names like "pci.7" which don't play well with using the
"-set device.$name.$prop=$value" options accessible to us via
<qemu:commandline> options. The solution is to add an <alias> to the
pcie-root-port <controller>, for example:
<controller type='pci' index='7' model='pcie-root-port'>
<model name='pcie-root-port'/>
<target chassis='7' port='0x15'/>
<alias name='ua-gfx0'/>
<address type='pci' domain='0x0000' bus='0x00' slot='0x02'
function='0x5'/>
</controller>
The "ua-" here is a mandatory prefix. We can then use:
<qemu:commandline>
<qemu:arg value='-set'/>
<qemu:arg value='device.ua-gfx0.speed=8'/>
<qemu:arg value='-set'/>
<qemu:arg value='device.ua-gfx0.width=16'/>
<qemu:arg value='-set'/>
</qemu:commandline>
Signed-off-by: Alex Williamson <address@hidden>
---
hw/pci-bridge/gen_pcie_root_port.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-bridge/gen_pcie_root_port.c
b/hw/pci-bridge/gen_pcie_root_port.c
index 299de429ec1e..e3bba2ab68ef 100644
--- a/hw/pci-bridge/gen_pcie_root_port.c
+++ b/hw/pci-bridge/gen_pcie_root_port.c
@@ -124,6 +124,8 @@ static Property gen_rp_props[] = {
res_reserve.mem_pref_32, -1),
DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
res_reserve.mem_pref_64, -1),
+ DEFINE_PROP_PCIE_LINK_SPEED("speed", PCIESlot, speed, PCIE_LINK_SPEED_2_5),
+ DEFINE_PROP_PCIE_LINK_WIDTH("width", PCIESlot, width, PCIE_LINK_WIDTH_1),
DEFINE_PROP_END_OF_LIST()
};
- [Qemu-devel] [RFC for-3.2 PATCH 0/7] pcie: Enhanced link speed and width support, Alex Williamson, 2018/11/14
- [Qemu-devel] [RFC for-3.2 PATCH 1/7] pcie: Create enums for link speed and width, Alex Williamson, 2018/11/14
- [Qemu-devel] [RFC for-3.2 PATCH 2/7] pci: Sync PCIe downstream port LNKSTA on read, Alex Williamson, 2018/11/14
- [Qemu-devel] [RFC for-3.2 PATCH 3/7] qapi: Define PCIe link speed and width properties, Alex Williamson, 2018/11/14
- [Qemu-devel] [RFC for-3.2 PATCH 4/7] pcie: Add link speed and width fields to PCIESlot, Alex Williamson, 2018/11/14
- [Qemu-devel] [RFC for-3.2 PATCH 5/7] pcie: Fill PCIESlot link fields to support higher speeds and widths, Alex Williamson, 2018/11/14
- [Qemu-devel] [RFC for-3.2 PATCH 6/7] pcie: Allow generic PCIe root port to specify link speed and width,
Alex Williamson <=
- [Qemu-devel] [RFC for-3.2 PATCH 7/7] vfio/pci: Remove PCIe Link Status emulation, Alex Williamson, 2018/11/14
- Re: [Qemu-devel] [RFC for-3.2 PATCH 0/7] pcie: Enhanced link speed and width support, no-reply, 2018/11/14
- Re: [Qemu-devel] [RFC for-3.2 PATCH 0/7] pcie: Enhanced link speed and width support, geoff, 2018/11/15