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[Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support |
Date: |
Thu, 15 Nov 2018 22:37:13 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
disas.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/disas.c b/disas.c
index 5325b7e6be..82a408f272 100644
--- a/disas.c
+++ b/disas.c
@@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size)
# ifdef _ARCH_PPC64
s.info.cap_mode = CS_MODE_64;
# endif
-#elif defined(__riscv__)
- print_insn = print_insn_riscv;
+#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
+#if defined(_ILP32)
+ print_insn = print_insn_riscv32;
+#elif defined(_LP64)
+ print_insn = print_insn_riscv64;
+#else
+#error unsupported RISC-V ABI
+#endif
#elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
print_insn = print_insn_arm_a64;
s.info.cap_arch = CS_ARCH_ARM64;
--
2.19.1
- Re: [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions, (continued)
- [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support,
Alistair Francis <=
- [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/11/15
- Re: [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support, no-reply, 2018/11/16