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Re: [Qemu-devel] [PATCH v6 08/13] hardfloat: implement float32/64 additi
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From: |
Emilio G. Cota |
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Subject: |
Re: [Qemu-devel] [PATCH v6 08/13] hardfloat: implement float32/64 addition and subtraction |
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Date: |
Tue, 4 Dec 2018 15:07:20 -0500 |
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User-agent: |
Mutt/1.9.4 (2018-02-28) |
On Tue, Dec 04, 2018 at 18:34:18 +0000, Alex Bennée wrote:
>
> Emilio G. Cota <address@hidden> writes:
(snip)
> > Note that the IBM and ARM machines benefit from having
> > HARDFLOAT_2F{32,64}_USE_FP set to 0. Otherwise their performance
> > can suffer significantly:
>
> Is this just the latency of pushing the number into a SIMD register and
> checking the flags compared to a bitmask check?
That's the case in the generated x86 assembly, so I presume
the same it's happening in the other ISAs (I didn't check
the assembly there).
(snip)
>
> Hmm the diff is confusing but the changes look fine in the final code:
>
> Reviewed-by: Alex Bennée <address@hidden>
Thanks!
E.