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[Qemu-devel] [PATCH v2 15/27] target/arm: Introduce arm_mmu_idx
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 15/27] target/arm: Introduce arm_mmu_idx |
Date: |
Thu, 13 Dec 2018 23:23:58 -0600 |
The pattern
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
is computing the full ARMMMUIdx, stripping off the ARM bits,
and then putting them back.
Avoid the extra two steps with the appropriate helper function.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
----
v2: Move arm_mmu_idx declaration to internals.h.
---
target/arm/cpu.h | 9 ++++++++-
target/arm/internals.h | 8 ++++++++
target/arm/helper.c | 27 ++++++++++++++++-----------
3 files changed, 32 insertions(+), 12 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6435997111..3cc7a069ce 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2747,7 +2747,14 @@ ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
-/* Determine the current mmu_idx to use for normal loads/stores */
+/**
+ * cpu_mmu_index:
+ * @env: The cpu environment
+ * @ifetch: True for code access, false for data access.
+ *
+ * Return the core mmu index for the current translation regime.
+ * This function is used by generic TCG code paths.
+ */
int cpu_mmu_index(CPUARMState *env, bool ifetch);
/* Indexes used when registering address spaces with cpu_address_space_init */
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 6bc0daf560..4a52fe58b6 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -912,4 +912,12 @@ void arm_cpu_update_virq(ARMCPU *cpu);
*/
void arm_cpu_update_vfiq(ARMCPU *cpu);
+/**
+ * arm_mmu_idx:
+ * @env: The cpu environment
+ *
+ * Return the full ARMMMUIdx for the current translation regime.
+ */
+ARMMMUIdx arm_mmu_idx(CPUARMState *env);
+
#endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 56960411e3..50c1db16dd 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7117,7 +7117,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t
lr, bool dotailchain,
limit = env->v7m.msplim[M_REG_S];
}
} else {
- mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+ mmu_idx = arm_mmu_idx(env);
frame_sp_p = &env->regs[13];
limit = v7m_sp_limit(env);
}
@@ -7298,7 +7298,7 @@ static bool v7m_push_stack(ARMCPU *cpu)
CPUARMState *env = &cpu->env;
uint32_t xpsr = xpsr_read(env);
uint32_t frameptr = env->regs[13];
- ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
/* Align stack pointer if the guest wants that */
if ((frameptr & 4) &&
@@ -11073,7 +11073,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs,
vaddr addr,
int prot;
bool ret;
ARMMMUFaultInfo fi = {};
- ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
*attrs = (MemTxAttrs) {};
@@ -12977,26 +12977,31 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState
*env, bool secstate)
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
}
-int cpu_mmu_index(CPUARMState *env, bool ifetch)
+ARMMMUIdx arm_mmu_idx(CPUARMState *env)
{
- int el = arm_current_el(env);
+ int el;
if (arm_feature(env, ARM_FEATURE_M)) {
- ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
-
- return arm_to_core_mmu_idx(mmu_idx);
+ return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
}
+ el = arm_current_el(env);
if (el < 2 && arm_is_secure_below_el3(env)) {
- return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
+ return ARMMMUIdx_S1SE0 + el;
+ } else {
+ return ARMMMUIdx_S12NSE0 + el;
}
- return el;
+}
+
+int cpu_mmu_index(CPUARMState *env, bool ifetch)
+{
+ return arm_to_core_mmu_idx(arm_mmu_idx(env));
}
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
- ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
int current_el = arm_current_el(env);
int fp_el = fp_exception_el(env, current_el);
uint32_t flags;
--
2.17.2
- [Qemu-devel] [PATCH v2 09/27] target/arm: Move helper_exception_return to helper-a64.c, (continued)
- [Qemu-devel] [PATCH v2 09/27] target/arm: Move helper_exception_return to helper-a64.c, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 10/27] target/arm: Add new_pc argument to helper_exception_return, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 02/27] target/arm: Add SCTLR bits through ARMv8.5, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 03/27] target/arm: Add PAuth active bit to tbflags, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 07/27] target/arm: Decode PAuth within disas_data_proc_1src, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pac), Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 11/27] target/arm: Rearrange decode in disas_uncond_b_reg, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 14/27] target/arm: Move cpu_mmu_index out of line, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 16/27] target/arm: Introduce arm_stage1_mmu_idx, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 12/27] target/arm: Decode PAuth within disas_uncond_b_reg, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 15/27] target/arm: Introduce arm_mmu_idx,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 17/27] target/arm: Create ARMVAParameters and helpers, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 22/27] target/arm: Implement pauth_addpac, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 21/27] target/arm: Implement pauth_auth, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 24/27] target/arm: Add PAuth system registers, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 18/27] target/arm: Reuse aa64_va_parameters for setting tbflags, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 25/27] target/arm: Enable PAuth for -cpu max, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 26/27] target/arm: Enable PAuth for user-only, part 2, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 20/27] target/arm: Implement pauth_strip, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 23/27] target/arm: Implement pauth_computepac, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 27/27] target/arm: Tidy TBI handling in gen_a64_set_pc, Richard Henderson, 2018/12/14