Re: [Qemu-devel] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder

[Richard Henderson]

On 12/19/18 11:19 AM, Alistair Francis wrote:
> +    case INDEX_op_ext32s_i64:
> +    case INDEX_op_extrl_i64_i32:
> +    case INDEX_op_extrh_i64_i32:
> +    case INDEX_op_ext_i32_i64:
> +        tcg_out_ext32s(s, a0, a1);
> +        break;

This is the last bug that's easy to identify.  It shows up quickly in a
linux-user smoke test [1].  Obviously extrl (extract low) and extrh (extract
high) should not be implemented identically.

Fixed thus.

With this, most of the tests pass, when run in a qemu-riscv chroot.  The ones
that don't primarily never get started.  E.g. the alpha test fails to map
ld.so, for reasons that I have not examined, since it's not a tcg problem.


r~


[1] https://archive.li/o/1YduE/wiki.qemu.org/download/linux-user-test-0.3.tar.gz


---
 tcg/riscv/tcg-target.inc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index f718542d63..6cf8de32b5 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -1614,11 +1614,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,

     case INDEX_op_ext32s_i64:
     case INDEX_op_extrl_i64_i32:
-    case INDEX_op_extrh_i64_i32:
     case INDEX_op_ext_i32_i64:
         tcg_out_ext32s(s, a0, a1);
         break;

+    case INDEX_op_extrh_i64_i32:
+        tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
+        break;
+
     case INDEX_op_mulsh_i32:
     case INDEX_op_mulsh_i64:
         tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
---