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[Qemu-devel] [PULL] RISC-V Updates for 3.2, Part 2


From: Palmer Dabbelt
Subject: [Qemu-devel] [PULL] RISC-V Updates for 3.2, Part 2
Date: Fri, 11 Jan 2019 10:06:26 -0800

The following changes since commit 147923b1a901a0370f83a0f4c58ec1baffef22f0:

  Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190108-pull-request' 
into staging (2019-01-08 16:07:32 +0000)

are available in the Git repository at:

  git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-3.2-part2

for you to fetch changes up to f7cdfa38f37e0985457ac03c3238861144a58b4c:

  default-configs: Enable USB support for RISC-V machines (2019-01-09 17:34:10 
-0800)

----------------------------------------------------------------
RISC-V Updates for 3.2, Part 2

This patch set contains a handful of Michael's CSR-related cleanups,
which should allow us to proceed with more outstanding bug fixes that
depend on them.

Additionally, there is a patch that turns on USB.  This works for me
when the kernel has the appropriate drivers (which will soon be in
defconfig) and I pass

    -device usb-ehci
    -drive id=my_usb_disk,file=usbdisk.img,if=none,format=raw
    -device usb-storage,drive=my_usb_disk

to QEMU.

----------------------------------------------------------------
Alistair Francis (1):
      default-configs: Enable USB support for RISC-V machines

Michael Clark (3):
      RISC-V: Implement modular CSR helper interface
      RISC-V: Implement atomic mip/sip CSR updates
      RISC-V: Implement existential predicates for CSRs

 default-configs/riscv32-softmmu.mak |   1 +
 default-configs/riscv64-softmmu.mak |   1 +
 target/riscv/Makefile.objs          |   2 +-
 target/riscv/cpu.c                  |   6 +
 target/riscv/cpu.h                  |  41 +-
 target/riscv/cpu_helper.c           |   7 +-
 target/riscv/csr.c                  | 863 ++++++++++++++++++++++++++++++++++++
 target/riscv/gdbstub.c              |  10 +-
 target/riscv/op_helper.c            | 613 +------------------------
 9 files changed, 935 insertions(+), 609 deletions(-)
 create mode 100644 target/riscv/csr.c




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