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[Qemu-devel] [PATCH 6/9] target/mips: Support the R5900 SQ multimedia in
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH 6/9] target/mips: Support the R5900 SQ multimedia instruction |
Date: |
Sun, 13 Jan 2019 20:06:51 +0100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 44 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 79505bb6c2..1c7c649d36 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2628,6 +2628,17 @@ static inline void gen_store_gpr (TCGv t, int reg)
#if defined(TARGET_MIPS64)
/* 128-bit multimedia register moves. */
+static inline void gen_load_mmr(TCGv_i64 hi, TCGv_i64 lo, int reg)
+{
+ if (reg == 0) {
+ tcg_gen_movi_i64(hi, 0);
+ tcg_gen_movi_i64(lo, 0);
+ } else {
+ tcg_gen_mov_i64(hi, cpu_mmr[reg]);
+ tcg_gen_mov_i64(lo, cpu_gpr[reg]);
+ }
+}
+
static inline void gen_store_mmr(TCGv_i64 hi, TCGv_i64 lo, int reg)
{
if (reg != 0) {
@@ -27512,7 +27523,36 @@ static void gen_mmi_lq(CPUMIPSState *env, DisasContext
*ctx)
static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_SQ */
+#if !defined(TARGET_MIPS64)
+ generate_exception_end(ctx, EXCP_RI);
+#else
+ TCGv_i64 addr = tcg_temp_new_i64();
+ TCGv_i64 val0 = tcg_temp_new_i64();
+ TCGv_i64 val1 = tcg_temp_new_i64();
+
+ gen_base_offset_addr(ctx, addr, base, offset);
+
+ /*
+ * The least significant four bits of the effective address are
+ * masked to zero, effectively creating an aligned address. No
+ * address exceptions due to alignment are possible.
+ */
+ tcg_gen_andi_i64(addr, addr, ~0xFULL);
+
+#if defined(TARGET_WORDS_BIGENDIAN)
+ gen_load_mmr(val0, val1, rt);
+#else
+ gen_load_mmr(val1, val0, rt);
+#endif
+
+ tcg_gen_qemu_st_i64(val0, addr, ctx->mem_idx, MO_UNALN | MO_64);
+ tcg_gen_addi_i64(addr, addr, 8);
+ tcg_gen_qemu_st_i64(val1, addr, ctx->mem_idx, MO_UNALN | MO_64);
+
+ tcg_temp_free_i64(val1);
+ tcg_temp_free_i64(val0);
+ tcg_temp_free_i64(addr);
+#endif /* defined(TARGET_MIPS64) */
}
/*
@@ -27540,7 +27580,7 @@ static void decode_mmi_sq(CPUMIPSState *env,
DisasContext *ctx)
{
int base = extract32(ctx->opcode, 21, 5);
int rt = extract32(ctx->opcode, 16, 5);
- int offset = extract32(ctx->opcode, 0, 16);
+ int offset = sextract32(ctx->opcode, 0, 16);
#ifdef CONFIG_USER_ONLY
uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
--
2.19.2
- [Qemu-devel] [PATCH 1/9] target/mips: Require TARGET_MIPS64 for R5900 multimedia instructions, (continued)
- [Qemu-devel] [PATCH 1/9] target/mips: Require TARGET_MIPS64 for R5900 multimedia instructions, Fredrik Noring, 2019/01/13
- [Qemu-devel] [PATCH 2/9] target/mips: Introduce 32 R5900 128-bit multimedia registers, Fredrik Noring, 2019/01/13
- [Qemu-devel] [PATCH 3/9] target/mips: Support the R5900 PCPYLD multimedia instruction, Fredrik Noring, 2019/01/13
- [Qemu-devel] [PATCH 4/9] target/mips: Support the R5900 PCPYUD multimedia instruction, Fredrik Noring, 2019/01/13
- [Qemu-devel] [PATCH 5/9] target/mips: Support the R5900 LQ multimedia instruction, Fredrik Noring, 2019/01/13
- [Qemu-devel] [PATCH 6/9] target/mips: Support the R5900 SQ multimedia instruction,
Fredrik Noring <=
- [Qemu-devel] [PATCH 7/9] tests/tcg/mips: Test R5900 multimedia instructions PCPYUD and PCPYLD, Fredrik Noring, 2019/01/13
- [Qemu-devel] [PATCH 8/9] tests/tcg/mips: Test R5900 multimedia instruction LQ, Fredrik Noring, 2019/01/13
- [Qemu-devel] [PATCH 9/9] tests/tcg/mips: Test R5900 multimedia instruction SQ, Fredrik Noring, 2019/01/13
- Re: [Qemu-devel] [PATCH 0/9] target/mips: Limited support for R5900 multimedia instructions, no-reply, 2019/01/13