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[Qemu-devel] [PULL 01/23] tcg: Add logical simplifications during gvec e
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 01/23] tcg: Add logical simplifications during gvec expand |
Date: |
Mon, 28 Jan 2019 07:58:45 -0800 |
We handle many of these during integer expansion, and the
rest of them during integer optimization.
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++++++-----
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 61c25f5784..ec231b78fb 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1840,7 +1840,12 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_and_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
- tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+
+ if (aofs == bofs) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+ } else {
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+ }
}
void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1853,7 +1858,12 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_or_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
- tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+
+ if (aofs == bofs) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+ } else {
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+ }
}
void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1866,7 +1876,12 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_xor_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
- tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+
+ if (aofs == bofs) {
+ tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
+ } else {
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+ }
}
void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1879,7 +1894,12 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_andc_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
- tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+
+ if (aofs == bofs) {
+ tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
+ } else {
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+ }
}
void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -1892,7 +1912,12 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs,
uint32_t aofs,
.opc = INDEX_op_orc_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
};
- tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+
+ if (aofs == bofs) {
+ tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
+ } else {
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+ }
}
static const GVecGen2s gop_ands = {
--
2.17.2
- [Qemu-devel] [PULL 00/23] tcg queued patches, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 01/23] tcg: Add logical simplifications during gvec expand,
Richard Henderson <=
- [Qemu-devel] [PULL 02/23] tcg: Add gvec expanders for nand, nor, eqv, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 03/23] tcg: Add write_aofs to GVecGen4, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 04/23] tcg: Add opcodes for vector saturated arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 05/23] tcg: Add opcodes for vector minmax arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 07/23] tcg/i386: Implement vector saturating arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 08/23] tcg/i386: Implement vector minmax arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 06/23] tcg/i386: Split subroutines out of tcg_expand_vec_op, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 09/23] tcg/aarch64: Implement vector saturating arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 10/23] tcg/aarch64: Implement vector minmax arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 22/23] tcg/tci: enable dynamic TLB sizing, Richard Henderson, 2019/01/28