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[Qemu-devel] [PULL 22/22] target/arm: Make FPSCR/FPCR trapped-exception
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/22] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI |
Date: |
Tue, 5 Feb 2019 17:05:10 +0000 |
The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for
enabling trapped IEEE floating point exceptions (where IEEE exception
conditions cause a CPU exception rather than updating the FPSR status
bits). QEMU doesn't implement this (and nor does the hardware we're
modelling), but for implementations which don't implement trapped
exception handling these control bits are supposed to be RAZ/WI.
This allows guest code to test for whether the feature is present
by trying to write to the bit and checking whether it sticks.
QEMU is incorrectly making these bits read as written. Make them
RAZ/WI as the architecture requires.
In particular this was causing problems for the NetBSD automatic
test suite.
Reported-by: Martin Husemann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 6 ++++++
target/arm/helper.c | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ec14d3e228d..47238e42458 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1418,6 +1418,12 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
#define FPSR_MASK 0xf800009f
#define FPCR_MASK 0x07ff9f00
+#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
+#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
+#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
+#define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
+#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
+#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index aaf5b0cd7ab..520ceea7a41 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12637,6 +12637,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t
val)
val &= ~FPCR_FZ16;
}
+ /*
+ * We don't implement trapped exception handling, so the
+ * trap enable bits are all RAZ/WI (not RES0!)
+ */
+ val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE);
+
changed = env->vfp.xregs[ARM_VFP_FPSCR];
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
env->vfp.vec_len = (val >> 16) & 7;
--
2.20.1
- [Qemu-devel] [PULL 19/22] hw/arm/boot: Factor out "set up firmware boot" code, (continued)
- [Qemu-devel] [PULL 19/22] hw/arm/boot: Factor out "set up firmware boot" code, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 12/22] target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 03/22] target/arm: Add BT and BTYPE to tb->flags, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 06/22] target/arm: Default handling of BTYPE during translation, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 16/22] gdbstub: allow killing QEMU via vKill command, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 11/22] tests/tcg/aarch64: Add pauth smoke test, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 05/22] target/arm: Cache the GP bit for a page in MemTxAttrs, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 22/22] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI,
Peter Maydell <=
- [Qemu-devel] [PULL 13/22] target/arm: Clean TBI for data operations in the translator, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 20/22] hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 17/22] hw/arm/boot: Fix block comment style in arm_load_kernel(), Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 18/22] hw/arm/boot: Factor out "direct kernel boot" code into its own function, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 08/22] target/arm: Set btype for indirect branches, Peter Maydell, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, no-reply, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, no-reply, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, no-reply, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, Peter Maydell, 2019/02/05