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[Qemu-devel] [PATCH v3 01/12] target/arm: Rely on optimization within tc
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 01/12] target/arm: Rely on optimization within tcg_gen_gvec_or |
Date: |
Fri, 8 Feb 2019 19:38:36 -0800 |
Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 6 +-----
target/arm/translate-sve.c | 6 +-----
target/arm/translate.c | 12 +++---------
3 files changed, 5 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e002251ac6..a12bfac719 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10648,11 +10648,7 @@ static void disas_simd_3same_logic(DisasContext *s,
uint32_t insn)
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
return;
case 2: /* ORR */
- if (rn == rm) { /* MOV */
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0);
- } else {
- gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
- }
+ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
return;
case 3: /* ORN */
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b15b615ceb..3a2eb51566 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -280,11 +280,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
{
- if (a->rn == a->rm) { /* MOV */
- return do_mov_z(s, a->rd, a->rn);
- } else {
- return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
- }
+ return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
}
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 66cf28c8cb..9d2dba7ed2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
- case 2:
- if (rn == rm) {
- /* VMOV */
- tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size);
- } else {
- /* VORR */
- tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
- vec_size, vec_size);
- }
+ case 2: /* VORR */
+ tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
+ vec_size, vec_size);
break;
case 3: /* VORN */
tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
--
2.17.2
- [Qemu-devel] [PATCH v3 00/12] target/arm: tcg vector cleanups, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 01/12] target/arm: Rely on optimization within tcg_gen_gvec_or,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 03/12] target/arm: Use vector minmax expanders for aarch32, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 02/12] target/arm: Use vector minmax expanders for aarch64, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 04/12] target/arm: Use tcg integer min/max primitives for neon, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 05/12] target/arm: Remove neon min/max helpers, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 07/12] target/arm: Fix arm_cpu_dump_state vs FPSCR, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 06/12] target/arm: Fix vfp_gdb_get/set_reg vs FPSCR, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 08/12] target/arm: Split out flags setting from vfp compares, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 11/12] target/arm: Use vector operations for saturation, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 09/12] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR], Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 10/12] target/arm: Split out FPSCR.QC to a vector field, Richard Henderson, 2019/02/08