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[Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr()
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr() |
Date: |
Wed, 13 Feb 2019 07:53:59 -0800 |
From: Bastian Koppelmann <address@hidden>
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 4a23372cb823..39af38081ede 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
- gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!riscv_has_ext(ctx->env, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c9a8fdda8a85..abdcd0631af4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -532,44 +532,6 @@ static void gen_jal(DisasContext *ctx, int rd,
target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!has_ext(ctx, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long bimm)
{
--
2.18.1
- [Qemu-devel] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, (continued)
- [Qemu-devel] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 04/35] target/riscv: Convert RV32I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr(),
Palmer Dabbelt <=
- [Qemu-devel] [PATCH v7 11/35] target/riscv: Convert RV64A insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 29/35] target/riscv: Remove gen_system(), Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/02/13