Re: [Qemu-devel] [PULL 00/27] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
1e820f425d gdbstub: Send a reply to the vKill packet.
4b56c889a3 target/arm: Add missing clear_tail calls
e1438456d4 target/arm: Use vector operations for saturation
a14a04e6bd target/arm: Split out FPSCR.QC to a vector field
b9fc85bc9f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
29d6aa1c6b target/arm: Split out flags setting from vfp compares
13dc2aabab target/arm: Fix arm_cpu_dump_state vs FPSCR
bc2c229b10 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
e53cd7d0b7 target/arm: Remove neon min/max helpers
bf7d4d099b target/arm: Use tcg integer min/max primitives for neon
c592edc6dd target/arm: Use vector minmax expanders for aarch32
cb8987e56a target/arm: Use vector minmax expanders for aarch64
f6edfc4342 target/arm: Rely on optimization within tcg_gen_gvec_or
45a5069fad hw/arm/armsse: Fix miswiring of expansion IRQs
eabbdbb6db hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
8f90489124 MAINTAINERS: Remove Peter Crosthwaite from various entries
43cd666a9e arm: Allow system registers for KVM guests to be changed by QEMU code
14ff7ecc19 linux-user/elfload: enable HWCAP_CPUID for AArch64
a3ad95ffd5 target/arm: expose remaining CPUID registers as RAZ
a72a7f23da target/arm: expose MPIDR_EL1 to userspace
5cff3370be target/arm: expose CPUID registers to userspace
56a00d6429 target/arm: relax permission checks for HWCAP_CPUID registers
4d6cbb28c5 target/arm: Restructure disas_fp_int_conv
3a6c8150ed target/arm: Force result size into dp after operation
58d010bbd1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
07c45234c3 target/arm: Implement HACR_EL2
4c11ba7a47 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

=== OUTPUT BEGIN ===
1/27 Checking commit 4c11ba7a474f (target/arm: Fix CRn to be 14 for 
PMEVTYPER/PMEVCNTR)
2/27 Checking commit 07c45234c380 (target/arm: Implement HACR_EL2)
3/27 Checking commit 58d010bbd1a4 (target/arm: Fix int128_make128 lo, hi order 
in paired_cmpxchg64_be)
4/27 Checking commit 3a6c8150ed4a (target/arm: Force result size into dp after 
operation)
5/27 Checking commit 4d6cbb28c5ba (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 56a00d6429b0 (target/arm: relax permission checks for 
HWCAP_CPUID registers)
7/27 Checking commit 5cff3370be15 (target/arm: expose CPUID registers to 
userspace)
8/27 Checking commit a72a7f23daec (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a3ad95ffd508 (target/arm: expose remaining CPUID registers 
as RAZ)
10/27 Checking commit 14ff7ecc19f0 (linux-user/elfload: enable HWCAP_CPUID for 
AArch64)
11/27 Checking commit 43cd666a9ee0 (arm: Allow system registers for KVM guests 
to be changed by QEMU code)
12/27 Checking commit 8f9048912404 (MAINTAINERS: Remove Peter Crosthwaite from 
various entries)
13/27 Checking commit eabbdbb6db70 (hw/intc/armv7m_nvic: Allow byte accesses to 
SHPR1)
14/27 Checking commit 45a5069fad23 (hw/arm/armsse: Fix miswiring of expansion 
IRQs)
15/27 Checking commit f6edfc43420c (target/arm: Rely on optimization within 
tcg_gen_gvec_or)
16/27 Checking commit cb8987e56aae (target/arm: Use vector minmax expanders for 
aarch64)
17/27 Checking commit c592edc6dd12 (target/arm: Use vector minmax expanders for 
aarch32)
18/27 Checking commit bf7d4d099b2c (target/arm: Use tcg integer min/max 
primitives for neon)
19/27 Checking commit e53cd7d0b768 (target/arm: Remove neon min/max helpers)
20/27 Checking commit bc2c229b10ce (target/arm: Fix vfp_gdb_get/set_reg vs 
FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+    case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;

ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+    case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;

total: 2 errors, 0 warnings, 16 lines checked

Patch 20/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

21/27 Checking commit 13dc2aabab5f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 29d6aa1c6b90 (target/arm: Split out flags setting from 
vfp compares)
23/27 Checking commit b9fc85bc9f7a (target/arm: Fix set of bits kept in 
xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14a04e6bde9 (target/arm: Split out FPSCR.QC to a vector 
field)
25/27 Checking commit e1438456d444 (target/arm: Use vector operations for 
saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+    TYPEN *d = vd, *n = vn; TYPEM *m = vm;                                 \
                                   ^

total: 1 errors, 0 warnings, 438 lines checked

Patch 25/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

26/27 Checking commit 4b56c889a3e1 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 1e820f425d28 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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