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[Qemu-devel] [PULL 28/50] target/ppc: Basic POWER9 bare-metal radix MMU
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 28/50] target/ppc: Basic POWER9 bare-metal radix MMU support |
Date: |
Tue, 26 Feb 2019 15:52:42 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
No guest support yet
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/mmu-radix64.c | 81 ++++++++++++++++++++++++++++++++++------
1 file changed, 69 insertions(+), 12 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index a07d757063..ca1fb2673f 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -31,10 +31,26 @@
static bool ppc_radix64_get_fully_qualified_addr(CPUPPCState *env, vaddr eaddr,
uint64_t *lpid, uint64_t *pid)
{
- /* We don't have HV support yet and shouldn't get here with it set anyway
*/
- assert(!msr_hv);
-
- if (!msr_hv) { /* !MSR[HV] -> Guest */
+ if (msr_hv) { /* MSR[HV] -> Hypervisor/bare metal */
+ switch (eaddr & R_EADDR_QUADRANT) {
+ case R_EADDR_QUADRANT0:
+ *lpid = 0;
+ *pid = env->spr[SPR_BOOKS_PID];
+ break;
+ case R_EADDR_QUADRANT1:
+ *lpid = env->spr[SPR_LPIDR];
+ *pid = env->spr[SPR_BOOKS_PID];
+ break;
+ case R_EADDR_QUADRANT2:
+ *lpid = env->spr[SPR_LPIDR];
+ *pid = 0;
+ break;
+ case R_EADDR_QUADRANT3:
+ *lpid = 0;
+ *pid = 0;
+ break;
+ }
+ } else { /* !MSR[HV] -> Guest */
switch (eaddr & R_EADDR_QUADRANT) {
case R_EADDR_QUADRANT0: /* Guest application */
*lpid = env->spr[SPR_LPIDR];
@@ -186,21 +202,32 @@ static uint64_t ppc_radix64_walk_tree(PowerPCCPU *cpu,
vaddr eaddr,
raddr, psize, fault_cause, pte_addr);
}
+static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
+{
+ CPUPPCState *env = &cpu->env;
+
+ if (!(pate->dw0 & PATE0_HR)) {
+ return false;
+ }
+ if (lpid == 0 && !msr_hv) {
+ return false;
+ }
+ /* More checks ... */
+ return true;
+}
+
int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ PPCVirtualHypervisorClass *vhc;
hwaddr raddr, pte_addr;
uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
int page_size, prot, fault_cause = 0;
ppc_v3_pate_t pate;
assert((rwx == 0) || (rwx == 1) || (rwx == 2));
- assert(!msr_hv); /* For now there is no Radix PowerNV Support */
- assert(cpu->vhyp);
assert(ppc64_use_proc_tbl(cpu));
/* Real Mode Access */
@@ -221,7 +248,23 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr, int rwx,
}
/* Get Process Table */
- vhc->get_pate(cpu->vhyp, &pate);
+ if (cpu->vhyp) {
+ vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->get_pate(cpu->vhyp, &pate);
+ } else {
+ if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
+ ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
+ return 1;
+ }
+ if (!validate_pate(cpu, lpid, &pate)) {
+ ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
+ }
+ /* We don't support guest mode yet */
+ if (lpid != 0) {
+ error_report("PowerNV guest support Unimplemented");
+ exit(1);
+ }
+ }
/* Index Process Table by PID to Find Corresponding Process Table Entry */
offset = pid * sizeof(struct prtb_entry);
@@ -256,8 +299,7 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu,
target_ulong eaddr)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ PPCVirtualHypervisorClass *vhc;
hwaddr raddr, pte_addr;
uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
int page_size, fault_cause = 0;
@@ -275,7 +317,22 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu,
target_ulong eaddr)
}
/* Get Process Table */
- vhc->get_pate(cpu->vhyp, &pate);
+ if (cpu->vhyp) {
+ vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->get_pate(cpu->vhyp, &pate);
+ } else {
+ if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
+ return -1;
+ }
+ if (!validate_pate(cpu, lpid, &pate)) {
+ return -1;
+ }
+ /* We don't support guest mode yet */
+ if (lpid != 0) {
+ error_report("PowerNV guest support Unimplemented");
+ exit(1);
+ }
+ }
/* Index Process Table by PID to Find Corresponding Process Table Entry */
offset = pid * sizeof(struct prtb_entry);
--
2.20.1
- [Qemu-devel] [PULL 12/50] cpus: Properly release the iothread lock when killing a dummy VCPU, (continued)
- [Qemu-devel] [PULL 12/50] cpus: Properly release the iothread lock when killing a dummy VCPU, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 18/50] target/ppc/spapr: Set LPCR:HR when using Radix mode, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 31/50] spapr: Generate FDT fragment for CPUs at configure connector time, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 17/50] tests/device-plug: Add memory unplug request test for spapr, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 21/50] target/ppc: Fix #include guard in mmu-book3s-v3.h, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 16/50] tests/device-plug: Add CPU core unplug request test for spapr, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 25/50] target/ppc: Flush the TLB locally when the LPIDR is written, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 23/50] target/ppc: Add basic support for "new format" HPTE as found on POWER9, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 26/50] target/ppc: Rename PATB/PATBE -> PATE, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 22/50] target/ppc: Fix ordering of hash MMU accesses, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 28/50] target/ppc: Basic POWER9 bare-metal radix MMU support,
David Gibson <=
- [Qemu-devel] [PULL 27/50] target/ppc: Support for POWER9 native hash, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 36/50] spapr_irq: Expose the phandle of the interrupt controller, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 30/50] spapr: Generate FDT fragment for LMBs at configure connector time, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 35/50] spapr: Expose the name of the interrupt controller node, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 29/50] spapr_drc: Allow FDT fragment to be added later, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 39/50] spapr: populate PHB DRC entries for root DT node, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 33/50] spapr/drc: Drop spapr_drc_attach() fdt argument, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 38/50] spapr: create DR connectors for PHBs, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 46/50] ppc/xive: xive does not have a POWER7 interrupt model, David Gibson, 2019/02/25
- [Qemu-devel] [PULL 50/50] ppc/pnv: use IEC binary prefixes to represent sizes, David Gibson, 2019/02/25