Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

[Amed Magdy]

>
>
>> > It seems to me that the C extension can be enabled at any point, since
>> if C is
>> > off, you know that the next insn is aligned modulo 4.
>> >
>>
>
>  > Ok, This is mostly right. When C extension is enabled 32-bit base
> instructions can be aligned on 2 bytes boundaries instead of 4 bytes only.
> > So multiple enables and disables of C bit at different code areas
> theoretically may require this check on C extension enable. I'm not really
> >sure, may be this is might not  be a practical use scenario.
>

 This paragraph considers the current implementation of csr write for misa
register.