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[PULL 3/6] hw/mips: Add CPU IRQ3 delivery for KVM
From: |
Aleksandar Markovic |
Subject: |
[PULL 3/6] hw/mips: Add CPU IRQ3 delivery for KVM |
Date: |
Mon, 1 Jun 2020 14:18:15 +0200 |
From: Huacai Chen <zltjiangshi@gmail.com>
Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
IP3 delivery as well, because Loongson-3 based machine use both IRQ2
(CPU's IP2) and IRQ3 (CPU's IP3).
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com>
---
hw/mips/mips_int.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 4a1bf84..0f9c6f0 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int
level)
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
}
- if (kvm_enabled() && irq == 2) {
+ if (kvm_enabled() && (irq == 2 || irq == 3)) {
kvm_mips_set_interrupt(cpu, irq, level);
}
--
2.7.4
- [PULL 0/6] MIPS queue for June 1st, 2020, Aleksandar Markovic, 2020/06/01
- [PULL 2/6] configure: Add KVM target support for MIPS64, Aleksandar Markovic, 2020/06/01
- [PULL 4/6] target/mips: Add more CP0 register for save/restore, Aleksandar Markovic, 2020/06/01
- [PULL 3/6] hw/mips: Add CPU IRQ3 delivery for KVM,
Aleksandar Markovic <=
- [PULL 1/6] tests/Makefile: Fix description of "make check", Aleksandar Markovic, 2020/06/01
- [PULL 5/6] target/mips: Support variable page size, Aleksandar Markovic, 2020/06/01
- [PULL 6/6] hw/mips: fuloong2e: Set preferred page size to 16KB, Aleksandar Markovic, 2020/06/01
- Re: [PULL 0/6] MIPS queue for June 1st, 2020, Peter Maydell, 2020/06/01