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[PULL 14/33] net: cadence_gem: Define access permission for interrupt re
From: |
Jason Wang |
Subject: |
[PULL 14/33] net: cadence_gem: Define access permission for interrupt registers |
Date: |
Tue, 16 Jun 2020 14:45:25 +0800 |
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Q1 to Q7 ISR's are clear-on-read, IER/IDR registers
are write-only, mask reg are read-only.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
---
hw/net/cadence_gem.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 4ad6c8e..72e7cf9 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -458,6 +458,7 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF };
*/
static void gem_init_register_masks(CadenceGEMState *s)
{
+ unsigned int i;
/* Mask of register bits which are read only */
memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
@@ -470,10 +471,19 @@ static void gem_init_register_masks(CadenceGEMState *s)
s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
+ for (i = 0; i < s->num_priority_queues; i++) {
+ s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF;
+ s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319;
+ s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319;
+ s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF;
+ }
/* Mask of register bits which are clear on read */
memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
+ for (i = 0; i < s->num_priority_queues; i++) {
+ s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6;
+ }
/* Mask of register bits which are write 1 to clear */
memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
@@ -485,6 +495,10 @@ static void gem_init_register_masks(CadenceGEMState *s)
s->regs_wo[GEM_NWCTRL] = 0x00073E60;
s->regs_wo[GEM_IER] = 0x07FFFFFF;
s->regs_wo[GEM_IDR] = 0x07FFFFFF;
+ for (i = 0; i < s->num_priority_queues; i++) {
+ s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6;
+ s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6;
+ }
}
/*
--
2.5.0
- [PULL 05/33] vmstate.h: provide VMSTATE_VARRAY_UINT16_ALLOC macro, (continued)
- [PULL 05/33] vmstate.h: provide VMSTATE_VARRAY_UINT16_ALLOC macro, Jason Wang, 2020/06/16
- [PULL 03/33] tap: allow extended virtio header with hash info, Jason Wang, 2020/06/16
- [PULL 02/33] virtio-net: implement RX RSS processing, Jason Wang, 2020/06/16
- [PULL 06/33] virtio-net: add migration support for RSS and hash report, Jason Wang, 2020/06/16
- [PULL 07/33] virtio-net: align RSC fields with updated virtio-net header, Jason Wang, 2020/06/16
- [PULL 09/33] hw/net/tulip: Fix 'Descriptor Error' definition, Jason Wang, 2020/06/16
- [PULL 10/33] hw/net/tulip: Log descriptor overflows, Jason Wang, 2020/06/16
- [PULL 08/33] Fix tulip breakage, Jason Wang, 2020/06/16
- [PULL 11/33] net: cadence_gem: Fix debug statements, Jason Wang, 2020/06/16
- [PULL 16/33] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState, Jason Wang, 2020/06/16
- [PULL 14/33] net: cadence_gem: Define access permission for interrupt registers,
Jason Wang <=
- [PULL 12/33] net: cadence_gem: Fix the queue address update during wrap around, Jason Wang, 2020/06/16
- [PULL 13/33] net: cadence_gem: Fix irq update w.r.t queue, Jason Wang, 2020/06/16
- [PULL 15/33] net: cadence_gem: Set ISR according to queue in use, Jason Wang, 2020/06/16
- [PULL 17/33] net: cadence_gem: Fix up code style, Jason Wang, 2020/06/16
- [PULL 18/33] net: cadence_gem: Add support for jumbo frames, Jason Wang, 2020/06/16
- [PULL 19/33] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg, Jason Wang, 2020/06/16
- [PULL 20/33] net: cadence_gem: Update the reset value for interrupt mask register, Jason Wang, 2020/06/16
- [PULL 22/33] net: cadence_gem: Fix RX address filtering, Jason Wang, 2020/06/16
- [PULL 21/33] net: cadence_gem: TX_LAST bit should be set by guest, Jason Wang, 2020/06/16
- [PULL 23/33] net: use peer when purging queue in qemu_flush_or_purge_queue_packets(), Jason Wang, 2020/06/16