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[PATCH v2 028/100] target/arm: Implement PMULLB and PMULLT
From: |
Richard Henderson |
Subject: |
[PATCH v2 028/100] target/arm: Implement PMULLB and PMULLT |
Date: |
Wed, 17 Jun 2020 21:25:32 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 10 ++++++++++
target/arm/helper-sve.h | 1 +
target/arm/sve.decode | 2 ++
target/arm/translate-sve.c | 22 ++++++++++++++++++++++
target/arm/vec_helper.c | 24 ++++++++++++++++++++++++
5 files changed, 59 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e9f56e67c7..f7574cb757 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3862,6 +3862,16 @@ static inline bool isar_feature_aa64_sve2(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
}
+static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
+}
+
+static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index cb1d4f2443..e7b539df21 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -1875,3 +1875,4 @@ DEF_HELPER_FLAGS_4(sve2_umull_zzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_umull_zzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_pmull_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 32370d7b76..079ba0ec62 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1204,6 +1204,8 @@ USUBWT 01000101 .. 0 ..... 010 111 ..... .....
@rd_rn_rm
SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm
SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm
+PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm
+PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm
SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm
SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm
UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 0712a25de7..db2081130d 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5596,6 +5596,28 @@ DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true)
DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false)
DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true)
+static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
+{
+ static gen_helper_gvec_3 * const fns[4] = {
+ gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h,
+ NULL, gen_helper_sve2_pmull_d,
+ };
+ if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) {
+ return false;
+ }
+ return do_sve2_zzw_ool(s, a, fns[a->esz], sel);
+}
+
+static bool trans_PMULLB(DisasContext *s, arg_rrr_esz *a)
+{
+ return do_trans_pmull(s, a, false);
+}
+
+static bool trans_PMULLT(DisasContext *s, arg_rrr_esz *a)
+{
+ return do_trans_pmull(s, a, true);
+}
+
#define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \
static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
{ \
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index cd58bfb84f..32b1aace3d 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -1378,6 +1378,30 @@ void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm,
uint32_t desc)
d[i] = pmull_h(nn, mm);
}
}
+
+static uint64_t pmull_d(uint64_t op1, uint64_t op2)
+{
+ uint64_t result = 0;
+ int i;
+
+ for (i = 0; i < 32; ++i) {
+ uint64_t mask = -((op1 >> i) & 1);
+ result ^= (op2 << i) & mask;
+ }
+ return result;
+}
+
+void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t sel = H4(simd_data(desc));
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ uint32_t *n = vn, *m = vm;
+ uint64_t *d = vd;
+
+ for (i = 0; i < opr_sz / 8; ++i) {
+ d[i] = pmull_d(n[2 * i + sel], m[2 * i + sel]);
+ }
+}
#endif
#define DO_CMP0(NAME, TYPE, OP) \
--
2.25.1
- [PATCH v2 019/100] target/arm: Split out saturating/rounding shifts from neon, (continued)
- [PATCH v2 019/100] target/arm: Split out saturating/rounding shifts from neon, Richard Henderson, 2020/06/18
- [PATCH v2 020/100] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 021/100] target/arm: Implement SVE2 integer halving add/subtract (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 022/100] target/arm: Implement SVE2 integer pairwise arithmetic, Richard Henderson, 2020/06/18
- [PATCH v2 023/100] target/arm: Implement SVE2 saturating add/subtract (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 024/100] target/arm: Implement SVE2 integer add/subtract long, Richard Henderson, 2020/06/18
- [PATCH v2 025/100] target/arm: Implement SVE2 integer add/subtract interleaved long, Richard Henderson, 2020/06/18
- [PATCH v2 026/100] target/arm: Implement SVE2 integer add/subtract wide, Richard Henderson, 2020/06/18
- [PATCH v2 029/100] target/arm: Tidy SVE tszimm shift formats, Richard Henderson, 2020/06/18
- [PATCH v2 027/100] target/arm: Implement SVE2 integer multiply long, Richard Henderson, 2020/06/18
- [PATCH v2 028/100] target/arm: Implement PMULLB and PMULLT,
Richard Henderson <=
- [PATCH v2 030/100] target/arm: Implement SVE2 bitwise shift left long, Richard Henderson, 2020/06/18
- [PATCH v2 033/100] target/arm: Implement SVE2 complex integer add, Richard Henderson, 2020/06/18
- [PATCH v2 034/100] target/arm: Implement SVE2 integer absolute difference and accumulate long, Richard Henderson, 2020/06/18
- [PATCH v2 035/100] target/arm: Implement SVE2 integer add/subtract long with carry, Richard Henderson, 2020/06/18
- [PATCH v2 036/100] target/arm: Implement SVE2 bitwise shift right and accumulate, Richard Henderson, 2020/06/18
- [PATCH v2 031/100] target/arm: Implement SVE2 bitwise exclusive-or interleaved, Richard Henderson, 2020/06/18
- [PATCH v2 032/100] target/arm: Implement SVE2 bitwise permute, Richard Henderson, 2020/06/18
- [PATCH v2 037/100] target/arm: Implement SVE2 bitwise shift and insert, Richard Henderson, 2020/06/18
- [PATCH v2 038/100] target/arm: Implement SVE2 integer absolute difference and accumulate, Richard Henderson, 2020/06/18
- [PATCH v2 039/100] target/arm: Implement SVE2 saturating extract narrow, Richard Henderson, 2020/06/18