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[PATCH v2 061/100] target/arm: Implement SVE2 gather load insns
From: |
Richard Henderson |
Subject: |
[PATCH v2 061/100] target/arm: Implement SVE2 gather load insns |
Date: |
Wed, 17 Jun 2020 21:26:05 -0700 |
From: Stephen Long <steplong@quicinc.com>
Add decoding logic for SVE2 64-bit/32-bit gather non-temporal
load insns.
64-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1SW
* LDNT1W (vector plus scalar)
* LDNT1D (vector plus scalar)
32-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1W (vector plus scalar)
Signed-off-by: Stephen Long <steplong@quicinc.com>
Message-Id: <20200422152343.12493-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 11 +++++++++++
target/arm/translate-sve.c | 8 ++++++++
2 files changed, 19 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index dc784dcabe..1b5bd2d193 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1389,6 +1389,17 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... .....
@rda_rn_rm
CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx
SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
+### SVE2 Memory Gather Load Group
+
+# SVE2 64-bit gather non-temporal load
+# (scalar plus unpacked 32-bit unscaled offsets)
+LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \
+ &rprr_gather_load xs=0 esz=3 scale=0 ff=0
+
+# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
+LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \
+ &rprr_gather_load xs=0 esz=2 scale=0 ff=0
+
### SVE2 Memory Store Group
# SVE2 64-bit scatter non-temporal store (vector plus scalar)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 7fa1e0d354..77003ee43e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5622,6 +5622,14 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz
*a)
return true;
}
+static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return trans_LDNT1_zprz(s, a);
+}
+
/* Indexed by [be][xs][msz]. */
static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][3] = {
/* Little-endian */
--
2.25.1
- [PATCH v2 050/100] target/arm: Generalize inl_qrdmlah_* helper functions, (continued)
- [PATCH v2 050/100] target/arm: Generalize inl_qrdmlah_* helper functions, Richard Henderson, 2020/06/18
- [PATCH v2 051/100] target/arm: Implement SVE2 saturating multiply-add high, Richard Henderson, 2020/06/18
- [PATCH v2 053/100] target/arm: Implement SVE2 complex integer multiply-add, Richard Henderson, 2020/06/18
- [PATCH v2 055/100] target/arm: Implement SVE2 RADDHNB, RADDHNT, Richard Henderson, 2020/06/18
- [PATCH v2 052/100] target/arm: Implement SVE2 integer multiply-add long, Richard Henderson, 2020/06/18
- [PATCH v2 054/100] target/arm: Implement SVE2 ADDHNB, ADDHNT, Richard Henderson, 2020/06/18
- [PATCH v2 056/100] target/arm: Implement SVE2 SUBHNB, SUBHNT, Richard Henderson, 2020/06/18
- [PATCH v2 059/100] target/arm: Implement SVE2 XAR, Richard Henderson, 2020/06/18
- [PATCH v2 057/100] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2020/06/18
- [PATCH v2 058/100] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2020/06/18
- [PATCH v2 061/100] target/arm: Implement SVE2 gather load insns,
Richard Henderson <=
- [PATCH v2 063/100] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2020/06/18
- [PATCH v2 060/100] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2020/06/18
- [PATCH v2 062/100] target/arm: Implement SVE2 FMMLA, Richard Henderson, 2020/06/18
- [PATCH v2 064/100] target/arm: Fix sve_uzp_p vs odd vector lengths, Richard Henderson, 2020/06/18
- [PATCH v2 065/100] target/arm: Fix sve_zip_p vs odd vector lengths, Richard Henderson, 2020/06/18
- [PATCH v2 066/100] target/arm: Fix sve_punpk_p vs odd vector lengths, Richard Henderson, 2020/06/18
- [PATCH v2 067/100] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2020/06/18
- [PATCH v2 068/100] target/arm: Pass separate addend to FCMLA helpers, Richard Henderson, 2020/06/18
- [PATCH v2 069/100] target/arm: Split out formats for 2 vectors + 1 index, Richard Henderson, 2020/06/18
- [PATCH v2 070/100] target/arm: Split out formats for 3 vectors + 1 index, Richard Henderson, 2020/06/18