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[PULL v2 02/32] sifive_e: Support the revB machine
From: |
Alistair Francis |
Subject: |
[PULL v2 02/32] sifive_e: Support the revB machine |
Date: |
Fri, 19 Jun 2020 09:57:47 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_e.h | 1 +
hw/riscv/sifive_e.c | 34 ++++++++++++++++++++++++++++++----
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index d386ea9223..637414130b 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -45,6 +45,7 @@ typedef struct SiFiveEState {
/*< public >*/
SiFiveESoCState soc;
+ bool revb;
} SiFiveEState;
#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1c17d02cf0..36486b72d2 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -95,10 +95,14 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2] = {
- 0x204002b7, /* 0x1000: lui t0,0x20400 */
- 0x00028067, /* 0x1004: jr t0 */
- };
+ uint32_t reset_vec[2];
+
+ if (s->revb) {
+ reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
+ } else {
+ reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
+ }
+ reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
@@ -112,8 +116,30 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ return s->revb;
+}
+
+static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = value;
+}
+
static void sifive_e_machine_instance_init(Object *obj)
{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = false;
+ object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
+ sifive_e_machine_set_revb);
+ object_property_set_description(obj, "revb",
+ "Set on to tell QEMU that it should model "
+ "the revB HiFive1 board");
}
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
--
2.27.0
- [PULL v2 00/32] riscv-to-apply queue, Alistair Francis, 2020/06/19
- [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register, Alistair Francis, 2020/06/19
- [PULL v2 14/32] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/06/19
- [PULL v2 15/32] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/06/19
- [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU, Alistair Francis, 2020/06/19
- [PULL v2 06/32] riscv: Keep the CPU init routine names consistent, Alistair Francis, 2020/06/19
- [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU, Alistair Francis, 2020/06/19
- [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL v2 02/32] sifive_e: Support the revB machine,
Alistair Francis <=
- [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/06/19
- [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU, Alistair Francis, 2020/06/19
- [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes, Alistair Francis, 2020/06/19
- [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19
- [PULL v2 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19