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Re: [PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for
From: |
Richard Henderson |
Subject: |
Re: [PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE |
Date: |
Thu, 25 Jun 2020 09:54:55 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 6/25/20 5:52 AM, Peter Maydell wrote:
> On Tue, 23 Jun 2020 at 20:37, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> There are a number of paths by which the TBI is still intact
>> for user-only in the SVE helpers.
>>
>> Because we currently always set TBI for user-only, we do not
>> need to pass down the actual TBI setting from above, and we
>> can remove the top byte in the inner-most primitives, so that
>> none are forgotten. Moreover, this keeps the "dirty" pointer
>> around at the higher levels, where we need it for any MTE checking.
>>
>> Since the normal case, especially for user-only, goes through
>> RAM, this clearing merely adds two insns per page lookup, which
>> will be completely in the noise.
>
> Can we have an assert() somewhere suitable that TBI is set?
> That way if we ever do have an SVE-capable linux-user which
> doesn't set TBI for some reason we'll get a useful reminder
> that we need to fix something.
At what level would you like such an assert?
At present we have, in arm_cpu_reset,
/*
* Enable TBI0 and TBI1. While the real kernel only enables TBI0,
* turning on both here will produce smaller code and otherwise
* make no difference to the user-level emulation.
*/
env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
r~
- [PATCH v8 34/45] target/arm: Add mte helpers for sve scalar + int stores, (continued)
- [PATCH v8 34/45] target/arm: Add mte helpers for sve scalar + int stores, Richard Henderson, 2020/06/23
- [PATCH v8 36/45] target/arm: Handle TBI for sve scalar + int memory ops, Richard Henderson, 2020/06/23
- [PATCH v8 33/45] target/arm: Add mte helpers for sve scalar + int loads, Richard Henderson, 2020/06/23
- [PATCH v8 35/45] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Richard Henderson, 2020/06/23
- [PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE, Richard Henderson, 2020/06/23
- [PATCH v8 40/45] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2020/06/23
- [PATCH v8 39/45] target/arm: Implement data cache set allocation tags, Richard Henderson, 2020/06/23
- [PATCH v8 37/45] target/arm: Add mte helpers for sve scatter/gather memory ops, Richard Henderson, 2020/06/23
- [PATCH v8 42/45] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2020/06/23
- [PATCH v8 41/45] target/arm: Always pass cacheattr to get_phys_addr, Richard Henderson, 2020/06/23
- [PATCH v8 43/45] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2020/06/23