[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 10/17] hw/block/nvme: add check for mdts
From: |
Klaus Jensen |
Subject: |
[PATCH 10/17] hw/block/nvme: add check for mdts |
Date: |
Mon, 29 Jun 2020 21:50:10 +0200 |
From: Klaus Jensen <k.jensen@samsung.com>
Add 'mdts' device parameter to control the Maximum Data Transfer Size of
the controller and check that it is respected.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
---
hw/block/nvme.c | 32 ++++++++++++++++++++++++++++++--
hw/block/nvme.h | 1 +
hw/block/trace-events | 1 +
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 7cd37ec91823..d5dff6869b69 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -18,9 +18,10 @@
* Usage: add options:
* -drive file=<file>,if=none,id=<drive_id>
* -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
- * cmb_size_mb=<cmb_size_mb[optional]>, \
+ * [cmb_size_mb=<cmb_size_mb>,] \
* [pmrdev=<mem_backend_file_id>,] \
- * max_ioqpairs=<N[optional]>
+ * [max_ioqpairs=<N>,] \
+ * [mdts=<N>]
*
* Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
* offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
@@ -518,6 +519,17 @@ static void nvme_clear_events(NvmeCtrl *n, uint8_t
event_type)
}
}
+static inline uint16_t nvme_check_mdts(NvmeCtrl *n, size_t len)
+{
+ uint8_t mdts = n->params.mdts;
+
+ if (mdts && len > n->page_size << mdts) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
+
+ return NVME_SUCCESS;
+}
+
static inline uint16_t nvme_check_bounds(NvmeCtrl *n, NvmeNamespace *ns,
uint64_t slba, uint32_t nlb)
{
@@ -611,6 +623,13 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns,
NvmeCmd *cmd,
trace_pci_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba);
+ status = nvme_check_mdts(n, data_size);
+ if (status) {
+ trace_pci_nvme_err_mdts(nvme_cid(req), data_size);
+ block_acct_invalid(blk_get_stats(n->conf.blk), acct);
+ return status;
+ }
+
status = nvme_check_bounds(n, ns, slba, nlb);
if (status) {
trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
@@ -904,6 +923,7 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeCmd *cmd,
NvmeRequest *req)
uint32_t numdl, numdu;
uint64_t off, lpol, lpou;
size_t len;
+ uint16_t status;
numdl = (dw10 >> 16);
numdu = (dw11 & 0xffff);
@@ -919,6 +939,12 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeCmd *cmd,
NvmeRequest *req)
trace_pci_nvme_get_log(nvme_cid(req), lid, lsp, rae, len, off);
+ status = nvme_check_mdts(n, len);
+ if (status) {
+ trace_pci_nvme_err_mdts(nvme_cid(req), len);
+ return status;
+ }
+
switch (lid) {
case NVME_LOG_ERROR_INFO:
return nvme_error_info(n, cmd, rae, len, off, req);
@@ -2227,6 +2253,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice
*pci_dev)
id->ieee[0] = 0x00;
id->ieee[1] = 0x02;
id->ieee[2] = 0xb3;
+ id->mdts = n->params.mdts;
id->ver = cpu_to_le32(NVME_SPEC_VER);
id->oacs = cpu_to_le16(0);
@@ -2345,6 +2372,7 @@ static Property nvme_props[] = {
DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl, params.msix_qsize, 65),
DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
+ DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 0169e1736f0c..b5ce51c6e84b 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -11,6 +11,7 @@ typedef struct NvmeParams {
uint32_t cmb_size_mb;
uint8_t aerl;
uint32_t aer_max_queued;
+ uint8_t mdts;
} NvmeParams;
typedef struct NvmeAsyncEvent {
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 6d0cd588c786..5d7d4679650b 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -85,6 +85,7 @@ pci_nvme_mmio_shutdown_set(void) "shutdown bit set"
pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared"
# nvme traces for error conditions
+pci_nvme_err_mdts(uint16_t cid, size_t len) "cid %"PRIu16" len %"PRIu64""
pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size"
pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or
not page aligned: 0x%"PRIx64""
pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned:
0x%"PRIx64""
--
2.27.0
- [PATCH 00/17] hw/block/nvme: AIO and address mapping refactoring, Klaus Jensen, 2020/06/29
- [PATCH 01/17] hw/block/nvme: memset preallocated requests structures, Klaus Jensen, 2020/06/29
- [PATCH 04/17] hw/block/nvme: remove redundant has_sg member, Klaus Jensen, 2020/06/29
- [PATCH 02/17] hw/block/nvme: add mapping helpers, Klaus Jensen, 2020/06/29
- [PATCH 03/17] hw/block/nvme: replace dma_acct with blk_acct equivalent, Klaus Jensen, 2020/06/29
- [PATCH 10/17] hw/block/nvme: add check for mdts,
Klaus Jensen <=
- [PATCH 05/17] hw/block/nvme: refactor dma read/write, Klaus Jensen, 2020/06/29
- [PATCH 06/17] hw/block/nvme: pass request along for tracing, Klaus Jensen, 2020/06/29
- [PATCH 08/17] hw/block/nvme: verify validity of prp lists in the cmb, Klaus Jensen, 2020/06/29
- [PATCH 07/17] hw/block/nvme: add request mapping helper, Klaus Jensen, 2020/06/29
- [PATCH 09/17] hw/block/nvme: refactor request bounds checking, Klaus Jensen, 2020/06/29
- [PATCH 11/17] hw/block/nvme: be consistent about zeros vs zeroes, Klaus Jensen, 2020/06/29
- [PATCH 13/17] hw/block/nvme: consolidate qsg/iov clearing, Klaus Jensen, 2020/06/29
- [PATCH 16/17] hw/block/nvme: add nvme_check_rw helper, Klaus Jensen, 2020/06/29
- [PATCH 14/17] hw/block/nvme: remove NvmeCmd parameter, Klaus Jensen, 2020/06/29
- [PATCH 17/17] hw/block/nvme: use preallocated qsg/iov in nvme_dma_prp, Klaus Jensen, 2020/06/29